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[209.85.128.41]) by smtp.gmail.com with ESMTPSA id n4-20020a056402060400b00415a1f9a4dasm1370944edv.91.2022.03.03.14.38.13 for (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 03 Mar 2022 14:38:13 -0800 (PST) Received: by mail-wm1-f41.google.com with SMTP id r187-20020a1c2bc4000000b003810e6b192aso4109323wmr.1 for ; Thu, 03 Mar 2022 14:38:13 -0800 (PST) X-Received: by 2002:a7b:c381:0:b0:37b:e01f:c1c0 with SMTP id s1-20020a7bc381000000b0037be01fc1c0mr5453850wmj.98.1646347092922; Thu, 03 Mar 2022 14:38:12 -0800 (PST) MIME-Version: 1.0 References: <1646300401-9063-1-git-send-email-quic_vpolimer@quicinc.com> <1646300401-9063-2-git-send-email-quic_vpolimer@quicinc.com> In-Reply-To: <1646300401-9063-2-git-send-email-quic_vpolimer@quicinc.com> From: Doug Anderson Date: Thu, 3 Mar 2022 14:38:00 -0800 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH v4 1/4] arm64/dts/qcom/sc7280: remove assigned-clock-rate property for mdp clk To: Vinod Polimera Cc: dri-devel , linux-arm-msm , freedreno , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , LKML , Rob Clark , Stephen Boyd , quic_kalyant@quicinc.com Content-Type: text/plain; charset="UTF-8" X-Spam-Status: No, score=-2.5 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi, On Thu, Mar 3, 2022 at 1:40 AM Vinod Polimera wrote: > > Kernel clock driver assumes that initial rate is the > max rate for that clock and was not allowing it to scale > beyond the assigned clock value. > > Drop the assigned clock rate property and vote on the mdp clock as per > calculated value during the usecase. I see the "Drop the assigned clock rate property" part, but where is the "and vote on the mdp clock" part? Did it already land or something? I definitely see that commit 5752c921d267 ("drm/msm/dpu: simplify clocks handling") changed a bunch of this but it looks like dpu_core_perf_init() still sets "max_core_clk_rate" to whatever the clock was at bootup. I assume you need to modify that function to call into the OPP layer to find the max frequency? > Changes in v2: > - Remove assigned-clock-rate property and set mdp clk during resume sequence. > - Add fixes tag. > > Changes in v3: > - Remove extra line after fixes tag.(Stephen Boyd) > > Fixes: 62fbdce91("arm64: dts: qcom: sc7280: add display dt nodes") Having a "Fixes" is good, but presumably you need a code change along with this, right? Otherwise if someone picks this back to stable then they'll end up breaking, right? We need to tag / note that _somehow_.