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Message-ID: <18137b0c-ef7e-bce7-b3bc-9e19d6f1d2c7@opensource.wdc.com>
Date:   Thu, 3 Mar 2022 18:09:03 +0200
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 Gecko/20100101 Thunderbird/91.6.1
Subject: Re: [PATCH 2/2] [RFC] ata: ahci: Skip debounce delay for AMD FCH SATA
 Controller
Content-Language: en-US
To:     Mario Limonciello <mario.limonciello@amd.com>,
        Paul Menzel <pmenzel@molgen.mpg.de>
Cc:     Hans de Goede <hdegoede@redhat.com>, linux-ide@vger.kernel.org,
        linux-kernel@vger.kernel.org
References: <20220303100453.30018-1-pmenzel@molgen.mpg.de>
 <20220303100453.30018-2-pmenzel@molgen.mpg.de>
 <0a7c8ee9-1e09-75a4-3241-883fc8540561@opensource.wdc.com>
 <edd464f1-916e-191a-3683-45b623604e4b@amd.com>
From:   Damien Le Moal <damien.lemoal@opensource.wdc.com>
Organization: Western Digital Research
In-Reply-To: <edd464f1-916e-191a-3683-45b623604e4b@amd.com>
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Precedence: bulk

On 2022/03/03 15:19, Mario Limonciello wrote:
> On 3/3/22 06:23, Damien Le Moal wrote:
>> On 2022/03/03 12:04, Paul Menzel wrote:
>>> AMD devices with the FCH SATA Controller 0x1022:0x7901 do not need th=
e
>>> default debounce delay of 200 ms.
>>>
>>>      07:00.2 SATA controller [0106]: Advanced Micro Devices, Inc. [AM=
D] FCH SATA Controller [AHCI mode] [1022:7901] (rev 51)
>>>
>>> So skip it, by mapping it to the board with no debounce delay.
>>>
>>> Tested on the MSI MS-7A37/B350M MORTAR (MS-7A37).
>>>
>>> To-do: Add test details and results.
>>
>> Please squash this patch together with patch 1. Since you are adding a=
 new board
>> entry definition, it is better to have a user for it in the same patch=
 (this
>> avoids reverts to leave unused code behind). >
>>>
>>> Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
>>> Cc: Hans de Goede <hdegoede@redhat.com>
>>> Cc: Mario Limonciello <mario.limonciello@amd.com>
>>> ---
>>> I am travelling so could not test this exact patch just yet, but I ra=
n
>>> something similar for several weeks already. It=E2=80=99d be great, i=
f the
>>> desktop and AMD folks could also give this a try.
>=20
> As we are trying to drop the low power definition for 5.18, maybe can=20
> this wait until 5.19 so we can see if that sticks so this doesn't get=20
> caught up in possible reverts?

The "no debounce delay" addition is a valid change regardless of the "low=
_power
is default" change. So I do not think this is an issue. But you will need=
 to
rebase your patch to include this change :)

Going forward, I would also like to have the "no debounce delay" as the d=
efault
too, after the low power default change settles and hopefully sticks.

>=20
>>>
>>>   drivers/ata/ahci.c | 2 +-
>>>   1 file changed, 1 insertion(+), 1 deletion(-)
>>>
>>> diff --git a/drivers/ata/ahci.c b/drivers/ata/ahci.c
>>> index 0fc09b86a559..44b79fe43d13 100644
>>> --- a/drivers/ata/ahci.c
>>> +++ b/drivers/ata/ahci.c
>>> @@ -456,7 +456,7 @@ static const struct pci_device_id ahci_pci_tbl[] =
=3D {
>>>   	{ PCI_VDEVICE(AMD, 0x7800), board_ahci }, /* AMD Hudson-2 */
>>>   	{ PCI_VDEVICE(AMD, 0x7801), board_ahci_no_debounce_delay }, /* AMD=
 Hudson-2 (AHCI mode) */
>>>   	{ PCI_VDEVICE(AMD, 0x7900), board_ahci }, /* AMD CZ */
>>> -	{ PCI_VDEVICE(AMD, 0x7901), board_ahci_low_power }, /* AMD Green Sa=
rdine */
>>> +	{ PCI_VDEVICE(AMD, 0x7901), board_ahci_low_power_no_debounce_delay =
}, /* AMD Green Sardine */
>>
>> Really long name, but I cannot think of anything better...
>>
>>>   	/* AMD is using RAID class only for ahci controllers */
>>>   	{ PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
>>>   	  PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci },
>>
>>
>=20


--=20
Damien Le Moal
Western Digital Research