Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20;
Date:   Fri, 04 Mar 2022 07:59:15 +0000
Message-ID: <87fsnytagc.wl-maz@kernel.org>
From:   Marc Zyngier <maz@kernel.org>
To:     Shawn Guo <shawn.guo@linaro.org>
Cc:     Thomas Gleixner <tglx@linutronix.de>,
        Maulik Shah <quic_mkshah@quicinc.com>,
        Bjorn Andersson <bjorn.andersson@linaro.org>,
        Sudeep Holla <sudeep.holla@arm.com>,
        Rob Herring <robh+dt@kernel.org>, devicetree@vger.kernel.org,
        linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH v7 2/2] irqchip: Add Qualcomm MPM controller driver
In-Reply-To: <20220303040229.GN269879@dragon>
References: <20220301062414.2987591-1-shawn.guo@linaro.org>
        <20220301062414.2987591-3-shawn.guo@linaro.org>
        <87ee3m2aed.wl-maz@kernel.org>
        <20220302084028.GL269879@dragon>
        <877d9c3b2u.wl-maz@kernel.org>
        <20220302133441.GM269879@dragon>
        <875yow31a0.wl-maz@kernel.org>
        <20220303040229.GN269879@dragon>
User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue)
 FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/27.1
 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO)
MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue")
Content-Type: text/plain; charset=US-ASCII
Precedence: bulk

On Thu, 03 Mar 2022 04:02:29 +0000,
Shawn Guo <shawn.guo@linaro.org> wrote:
> 
> On Wed, Mar 02, 2022 at 01:57:27PM +0000, Marc Zyngier wrote:
> > This code actually makes me ask more questions. Why is it programming
> > 2 'pins' for each IRQ?
> 
> The mapping between MPM pin and GIC IRQ is not strictly 1-1.  There are
> some rare case that up to 2 MPM pins map to a single GIC IRQ, for
> example the last two in QC2290 'qcom,mpm-pin-map' below.
> 
> 	qcom,mpm-pin-map = <2 275>,     /* tsens0_tsens_upper_lower_int */
> 			   <5 296>,     /* lpass_irq_out_sdc */
> 			   <12 422>,    /* b3_lfps_rxterm_irq */
> 			   <24 79>,     /* bi_px_lpi_1_aoss_mx */
> 			   <86 183>,    /* mpm_wake,spmi_m */
> 			   <90 260>,    /* eud_p0_dpse_int_mx */
> 			   <91 260>;    /* eud_p0_dmse_int_mx */
> 
> 
> The downstream uses a DT bindings that specifies GIC hwirq number in
> client device nodes.  In that case, d->hwirq in the driver is GIC IRQ
> number, and the driver will need to query mapping table, find out the
> possible 2 MPM pins, and set them up.
> 
> The patches I'm posting here use a different bindings that specifies MPM
> pin instead in client device nodes.  Thus the driver can simply get the
> MPM pin from d->hwirq, so that the whole look-up procedure can be saved.

It still remains that there is no 1:1 mapping between input and
output, which is the rule #1 to be able to use a hierarchical setup.

/me puzzled.

>
> > 
> > > 
> > > It seems MPM_REG_POLARITY is only meant for level interrupts, since edge
> > > interrupts already have separate registers for rising and falling.
> > 
> > Then level interrupts must clear both the edge registers at all times.
> 
> The downstream logic already covers that, right?  The edge register bits
> will be cleared as long as 'flowtype' is not EDGE.

I am talking about *your* code, not the Qualcomm stuff.

	M.

-- 
Without deviation from the norm, progress is not possible.