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[209.85.221.48]) by smtp.gmail.com with ESMTPSA id r11-20020aa7cfcb000000b00412c58c43ccsm1328830edy.37.2022.03.03.13.52.21 for (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 03 Mar 2022 13:52:21 -0800 (PST) Received: by mail-wr1-f48.google.com with SMTP id d3so9854218wrf.1 for ; Thu, 03 Mar 2022 13:52:21 -0800 (PST) X-Received: by 2002:a5d:64ed:0:b0:1f0:6672:f10c with SMTP id g13-20020a5d64ed000000b001f06672f10cmr1142174wri.679.1646344341238; Thu, 03 Mar 2022 13:52:21 -0800 (PST) MIME-Version: 1.0 References: <20220303015151.1711860-1-pgwipeout@gmail.com> In-Reply-To: <20220303015151.1711860-1-pgwipeout@gmail.com> From: Doug Anderson Date: Thu, 3 Mar 2022 13:52:08 -0800 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH] mmc: host: dw-mmc-rockchip: fix handling invalid clock rates To: Peter Geis Cc: Robin Murphy , Jaehoon Chung , Ulf Hansson , Heiko Stuebner , Addy Ke , Linux MMC List , Linux ARM , "open list:ARM/Rockchip SoC..." , LKML Content-Type: text/plain; charset="UTF-8" X-Spam-Status: No, score=-2.5 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi, On Wed, Mar 2, 2022 at 5:52 PM Peter Geis wrote: > > The Rockchip ciu clock cannot be set as low as the dw-mmc hardware > supports. This leads to a situation during card initialization where the > ciu clock is set lower than the clock driver can support. The > dw-mmc-rockchip driver spews errors when this happens. > For normal operation this only happens a few times during boot, but when > cd-broken is enabled (in cases such as the SoQuartz module) this fires > multiple times each poll cycle. > > Fix this by testing the minimum frequency the clock driver can support > that is within the mmc specification, then divide that by the internal > clock divider. Set the f_min frequency to this value, or if it fails, > set f_min to the downstream driver's default. > > Fixes: f629ba2c04c9 ("mmc: dw_mmc: add support for RK3288") I don't spend tons of time either Rockchip or dw-mmc these days, but your email tickled a memory in my mind and I swore that I remember this whole 400 kHz minimum thing, though I never dug into it myself. It actually looks like the 400 kHz minimum disappeared sometime in 2016! See commit 6a8883d614c7 ("ARM: dts: rockchip: replace to "max-frequency" instead of "clock-freq-min-max"") which only accounted for the high end, not the low end? I'm pretty sure I've tested on veyron since then, though and I didn't see any errors, but perhaps this is because I was never using cd-broken and the 400 kHz always worked? -Doug