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Fri, 4 Mar 2022 06:58:21 +0000 Received: from xsj-pvapexch02.xlnx.xilinx.com (172.19.86.41) by xsj-pvapexch02.xlnx.xilinx.com (172.19.86.41) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.14; Thu, 3 Mar 2022 22:58:20 -0800 Received: from smtp.xilinx.com (172.19.127.95) by xsj-pvapexch02.xlnx.xilinx.com (172.19.86.41) with Microsoft SMTP Server id 15.1.2176.14 via Frontend Transport; Thu, 3 Mar 2022 22:58:20 -0800 Envelope-to: git@xilinx.com, robert.hancock@calian.com, linux-kernel@vger.kernel.org, monstr@monstr.eu, maz@kernel.org, tglx@linutronix.de, linux-arm-kernel@lists.infradead.org Received: from [10.254.241.50] (port=37780) by smtp.xilinx.com with esmtp (Exim 4.90) (envelope-from ) id 1nQ1tM-0006Em-60; Thu, 03 Mar 2022 22:58:20 -0800 Message-ID: <92ca12e2-9efd-702e-6940-7fcdc873da7b@xilinx.com> Date: Fri, 4 Mar 2022 07:58:17 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.6.1 Subject: Re: [PATCH] irqchip: xilinx: Enable generic irq multi handler Content-Language: en-US To: Robert Hancock , "linux-kernel@vger.kernel.org" , "michal.simek@xilinx.com" , "git@xilinx.com" , "monstr@monstr.eu" CC: "maz@kernel.org" , "tglx@linutronix.de" , "linux-arm-kernel@lists.infradead.org" , "stefan.asserhall@xilinx.com" References: <2a08d6c33e95d5da5d564ed3fbddc835983ef355.1646323896.git.michal.simek@xilinx.com> <32881b5e94487845874b78dd36bbb5edec683e75.camel@calian.com> From: Michal Simek In-Reply-To: <32881b5e94487845874b78dd36bbb5edec683e75.camel@calian.com> Content-Type: text/plain; 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X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Mar 2022 06:58:21.9360 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 71e98936-1a20-48e1-85da-08d9fdac5f09 X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c;Ip=[149.199.62.198];Helo=[xsj-pvapexch02.xlnx.xilinx.com] X-MS-Exchange-CrossTenant-AuthSource: DM3NAM02FT012.eop-nam02.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY4PR02MB2823 X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, NICE_REPLY_A,RDNS_NONE,SPF_HELO_NONE,T_SCC_BODY_TEXT_LINE autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 3/3/22 18:01, Robert Hancock wrote: > On Thu, 2022-03-03 at 17:11 +0100, Michal Simek wrote: >> Register default arch handler via driver instead of directly pointing to >> xilinx intc controller. This patch makes architecture code more generic. >> >> Signed-off-by: Michal Simek >> Reviewed-by: Stefan Asserhall >> --- >> >> arch/microblaze/Kconfig | 2 ++ >> arch/microblaze/include/asm/irq.h | 3 --- >> arch/microblaze/kernel/irq.c | 16 +--------------- >> drivers/irqchip/irq-xilinx-intc.c | 22 +++++++++++++++++++++- >> 4 files changed, 24 insertions(+), 19 deletions(-) >> >> diff --git a/arch/microblaze/Kconfig b/arch/microblaze/Kconfig >> index 59798e43cdb0..da568e981604 100644 >> --- a/arch/microblaze/Kconfig >> +++ b/arch/microblaze/Kconfig >> @@ -45,6 +45,8 @@ config MICROBLAZE >> select SET_FS >> select ZONE_DMA >> select TRACE_IRQFLAGS_SUPPORT >> + select GENERIC_IRQ_MULTI_HANDLER >> + select HANDLE_DOMAIN_IRQ >> >> # Endianness selection >> choice >> diff --git a/arch/microblaze/include/asm/irq.h >> b/arch/microblaze/include/asm/irq.h >> index 0a28e80bbab0..cb6ab55d1d01 100644 >> --- a/arch/microblaze/include/asm/irq.h >> +++ b/arch/microblaze/include/asm/irq.h >> @@ -11,7 +11,4 @@ >> struct pt_regs; >> extern void do_IRQ(struct pt_regs *regs); >> >> -/* should be defined in each interrupt controller driver */ >> -extern unsigned int xintc_get_irq(void); >> - >> #endif /* _ASM_MICROBLAZE_IRQ_H */ >> diff --git a/arch/microblaze/kernel/irq.c b/arch/microblaze/kernel/irq.c >> index 903dad822fad..1f8cb4c4f74f 100644 >> --- a/arch/microblaze/kernel/irq.c >> +++ b/arch/microblaze/kernel/irq.c >> @@ -20,27 +20,13 @@ >> #include >> #include >> >> -static u32 concurrent_irq; >> - >> void __irq_entry do_IRQ(struct pt_regs *regs) >> { >> - unsigned int irq; >> struct pt_regs *old_regs = set_irq_regs(regs); >> trace_hardirqs_off(); >> >> irq_enter(); >> - irq = xintc_get_irq(); >> -next_irq: >> - BUG_ON(!irq); >> - generic_handle_irq(irq); >> - >> - irq = xintc_get_irq(); >> - if (irq != -1U) { >> - pr_debug("next irq: %d\n", irq); >> - ++concurrent_irq; >> - goto next_irq; >> - } >> - >> + handle_arch_irq(regs); >> irq_exit(); >> set_irq_regs(old_regs); >> trace_hardirqs_on(); >> diff --git a/drivers/irqchip/irq-xilinx-intc.c b/drivers/irqchip/irq-xilinx- >> intc.c >> index 356a59755d63..c6710190c152 100644 >> --- a/drivers/irqchip/irq-xilinx-intc.c >> +++ b/drivers/irqchip/irq-xilinx-intc.c >> @@ -110,7 +110,7 @@ static struct irq_chip intc_dev = { >> .irq_mask_ack = intc_mask_ack, >> }; >> >> -unsigned int xintc_get_irq(void) >> +static unsigned int xintc_get_irq(void) >> { >> unsigned int irq = -1; >> u32 hwirq; >> @@ -164,6 +164,25 @@ static void xil_intc_irq_handler(struct irq_desc *desc) >> chained_irq_exit(chip, desc); >> } >> >> +static u32 concurrent_irq; > > Not sure what this variable is for? It seems to be incremented, but never read. I used this when I was checking how irqs are working and how many concurrent_irq I am getting. It was read via debugger not via any linux interface. Thanks, Michal