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Fri, 04 Mar 2022 10:07:24 -0800 (PST) X-Received: by 2002:a37:e209:0:b0:648:b0eb:3bab with SMTP id g9-20020a37e209000000b00648b0eb3babmr3388608qki.229.1646417244016; Fri, 04 Mar 2022 10:07:24 -0800 (PST) Received: from treble ([2600:1700:6e32:6c00::45]) by smtp.gmail.com with ESMTPSA id d15-20020a05622a15cf00b002de711a190bsm3817117qty.71.2022.03.04.10.07.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Mar 2022 10:07:23 -0800 (PST) Date: Fri, 4 Mar 2022 10:07:20 -0800 From: Josh Poimboeuf To: Peter Zijlstra Cc: x86@kernel.org, joao@overdrivepizza.com, hjl.tools@gmail.com, andrew.cooper3@citrix.com, linux-kernel@vger.kernel.org, ndesaulniers@google.com, keescook@chromium.org, samitolvanen@google.com, mark.rutland@arm.com, alyssa.milburn@intel.com, mbenes@suse.cz, rostedt@goodmis.org, mhiramat@kernel.org, alexei.starovoitov@gmail.com Subject: Re: [PATCH v3 22/39] x86/ibt: Add IBT feature, MSR and #CP handling Message-ID: <20220304180720.qkvvjtsbbnfugxxy@treble> References: <20220303112321.422525803@infradead.org> <20220303112826.299051388@infradead.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline In-Reply-To: <20220303112826.299051388@infradead.org> X-Spam-Status: No, score=-2.3 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,RDNS_NONE,SPF_HELO_NONE,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, Mar 03, 2022 at 12:23:43PM +0100, Peter Zijlstra wrote: > @@ -310,6 +311,7 @@ void machine_kexec(struct kimage *image) > /* Interrupts aren't acceptable while we reboot */ > local_irq_disable(); > hw_breakpoint_disable(); > + cet_disable(); > > if (image->preserve_context) { > #ifdef CONFIG_X86_IO_APIC > --- a/arch/x86/kernel/relocate_kernel_64.S > +++ b/arch/x86/kernel/relocate_kernel_64.S > @@ -115,6 +115,14 @@ SYM_CODE_START_LOCAL_NOALIGN(identity_ma > pushq %rdx > > /* > + * Clear X86_CR4_CET (if it was set) such that we can clear CR0_WP > + * below. > + */ > + movq %cr4, %rax > + andq $~(X86_CR4_CET), %rax > + movq %rax, %cr4 > + > + /* > * Set cr0 to a known state: > * - Paging enabled > * - Alignment check disabled This probably belongs in a separate patch... -- Josh