Received: by 2002:a19:6e46:0:0:0:0:0 with SMTP id q6csp392397lfk; Fri, 4 Mar 2022 14:39:15 -0800 (PST) X-Google-Smtp-Source: ABdhPJwSvXHOqs6kGnSKCW4SoX3JPidoNV+MTlXzIVGb5q+5hdhX3udFbwZvOnHOYg1d0cVsXCrX X-Received: by 2002:a17:90b:3b42:b0:1bf:b72:30e9 with SMTP id ot2-20020a17090b3b4200b001bf0b7230e9mr11509895pjb.135.1646433554800; Fri, 04 Mar 2022 14:39:14 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1646433554; cv=none; d=google.com; s=arc-20160816; b=BekSCz5ftPR9EVbugwI9+MBypKED1l3yZFVS0Sm8geMlBxPWONL1NpirmNQEbZpGND kQN5fFS1DnPMLVUx/Mh8ndjRgQ0IgYhKrBu0TRsupFkD/SHr/pdGFhVMsrV1cjhGnOoD uJ7yFrt+4j8nnX6+47st1kuLfI1c2GRE6LEQx/tswKjttZXkYfum/PvSxYW3FEcI2e+u JKOZUbKMeezGBv6BSpvdbtV87/UbA2j/0v+Z4aXkIb0OZZbF6I8h6oTkX1rjzGR3w7sB d1cLEpfMPHU8WP4jNGU/j9+E501i9kDPzRCz3/sRJ6Z77pMQMmvG8uYVcfsxH4jTL/3M Qpbg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:dkim-signature:message-id:date:subject:cc:to :from; bh=8QQF6dKhkO+Z5X7/e+vXsxFm9xV9/q6QSNG67LdjZHs=; b=XvcKT7FhhPR/yKi/cdLLjUjmuWBt+nM/WQtaVQvIYhe9KrFjcUcABKnUiKmkJcuDHJ VhCfUEAW9qFo2IJ3FJ+PFZ8izyvBjr0pAlfA0R5xYz9LdJ33zPqT/OyijFDfbb+jmoBB ICAOXSF7j5Gc4lfO5MU33+DHx/keLE9jzRZKo/qrH8V9lKVsjg6ABzuvgseaK146Dc/Q 4BW2aMiW6tOp90SGV6A1Y0gNglSJyEyBAvJX9vmDW61HEeXajl+tcw9GV3c6cB08DgLu Zjpeq/aVqROd2rHc+zE5AvrO/34XCP+HgsDskjyOvu+VeN9/2Wl3KO3qho7nv59i2ww+ Mi1A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@embeddedTS.com header.s=mailanyone20220121 header.b=fODEx0ph; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=embeddedts.com Return-Path: Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id e19-20020a63e013000000b00362a575c68csi5744466pgh.795.2022.03.04.14.38.47; Fri, 04 Mar 2022 14:39:14 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@embeddedTS.com header.s=mailanyone20220121 header.b=fODEx0ph; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=embeddedts.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229892AbiCDWUw (ORCPT + 99 others); Fri, 4 Mar 2022 17:20:52 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43162 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229468AbiCDWUv (ORCPT ); Fri, 4 Mar 2022 17:20:51 -0500 X-Greylist: delayed 269 seconds by postgrey-1.37 at lindbergh.monkeyblade.net; Fri, 04 Mar 2022 14:20:03 PST Received: from smtp-out3.electric.net (smtp-out3.electric.net [208.70.128.188]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4740115B980 for ; Fri, 4 Mar 2022 14:20:03 -0800 (PST) Received: from 1nQGCy-0002oo-VO by out3b.electric.net with emc1-ok (Exim 4.94.2) (envelope-from ) id 1nQGCz-0002s3-Vq; Fri, 04 Mar 2022 14:15:33 -0800 Received: by emcmailer; Fri, 04 Mar 2022 14:15:33 -0800 Received: from [66.210.251.27] (helo=mail.embeddedts.com) by out3b.electric.net with esmtps (TLS1.2) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1nQGCy-0002oo-VO; Fri, 04 Mar 2022 14:15:32 -0800 Received: from tsdebian.ts-local.net (_gateway [192.168.0.64]) by mail.embeddedts.com (Postfix) with ESMTPSA id 017173A8F8; Fri, 4 Mar 2022 15:15:31 -0700 (MST) From: Kris Bahnsen To: Linus Walleij , Bartosz Golaszewski , linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Mark Featherston , Kris Bahnsen Subject: [PATCH] gpio: ts4900: Do not set DAT and OE together Date: Fri, 4 Mar 2022 14:15:17 -0800 Message-Id: <20220304221517.30213-1-kris@embeddedTS.com> X-Mailer: git-send-email 2.11.0 X-Outbound-IP: 66.210.251.27 X-Env-From: kris@embeddedTS.com X-Proto: esmtps X-Revdns: wsip-66-210-251-27.ph.ph.cox.net X-HELO: mail.embeddedts.com X-TLS: TLS1.2:ECDHE-RSA-AES256-GCM-SHA384:256 X-Authenticated_ID: X-Virus-Status: Scanned by VirusSMART (c) X-Virus-Status: Scanned by VirusSMART (b) X-FM-Delivery-Delay: 15749372,23518412 X-PolicySMART: 13164782, 15749372, 26810492 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=embeddedTS.com; s=mailanyone20220121;h=Message-Id:Date:To:From; bh=8QQF6dKhkO+Z5X7/e+vXsxFm9xV9/q6QSNG67LdjZHs=;b=fODEx0ph/I0Bo9UrO6oHYrSzq7nqFvuhsC2DLPJLZRzQ+jhRuHD7OaGm9NrZgt9C1ihCBnqHWwiXNiGjZ/JQbEogu+ADftMAzT4L5W1A0AEHVpCQgxpx1ZMwUzEq8ELQZ5ihBMmpRROsVza1kHH9dvAno67zrapBtTn/fRKddWLRKzjVbVIQgmH4euVmFPVjW57KwTMS3k6YZ+wwqV9slbi3NW0LW3KQjkKP1n3ccsPoIrr4p80iYVu1KHrjNbnkkYTCiNRXUAqEdVHiZWH6UDjVTkdZwWxWpk2ssrRoj3qa6yGrsC3eRLQNmW/X0uJyJ70lxh4rOK/vGpCsl1tnjQ==; X-FM-Delivery-Delay: 15749372,23518412 X-PolicySMART: 13164782, 15749372, 26810492 X-FM-Delivery-Delay: 15749372,23518412 X-PolicySMART: 13164782, 15749372, 26810492 X-FM-Delivery-Delay: 15749372,23518412 X-PolicySMART: 13164782, 15749372, 26810492 X-Spam-Status: No, score=-2.8 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_LOW,SPF_HELO_PASS, SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Mark Featherston This works around an issue with the hardware where both OE and DAT are exposed in the same register. If both are updated simultaneously, the harware makes no guarantees that OE or DAT will actually change in any given order and may result in a glitch of a few ns on a GPIO pin when changing direction and value in a single write. Setting direction to input now only affects OE bit. Setting direction to output updates DAT first, then OE. Signed-off-by: Mark Featherston Signed-off-by: Kris Bahnsen --- drivers/gpio/gpio-ts4900.c | 25 ++++++++++++++++++++----- 1 file changed, 20 insertions(+), 5 deletions(-) diff --git a/drivers/gpio/gpio-ts4900.c b/drivers/gpio/gpio-ts4900.c index d885032cf814..fbabfca030c0 100644 --- a/drivers/gpio/gpio-ts4900.c +++ b/drivers/gpio/gpio-ts4900.c @@ -1,7 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Digital I/O driver for Technologic Systems I2C FPGA Core * - * Copyright (C) 2015 Technologic Systems + * Copyright (C) 2015-2018 Technologic Systems * Copyright (C) 2016 Savoir-Faire Linux * * This program is free software; you can redistribute it and/or @@ -55,19 +56,33 @@ static int ts4900_gpio_direction_input(struct gpio_chip *chip, { struct ts4900_gpio_priv *priv = gpiochip_get_data(chip); - /* - * This will clear the output enable bit, the other bits are - * dontcare when this is cleared + /* Only clear the OE bit here, requires a RMW. Prevents potential issue + * with OE and data getting to the physical pin at different times. */ - return regmap_write(priv->regmap, offset, 0); + return regmap_update_bits(priv->regmap, offset, TS4900_GPIO_OE, 0); } static int ts4900_gpio_direction_output(struct gpio_chip *chip, unsigned int offset, int value) { struct ts4900_gpio_priv *priv = gpiochip_get_data(chip); + unsigned int reg; int ret; + /* If changing from an input to an output, we need to first set the + * proper data bit to what is requested and then set OE bit. This + * prevents a glitch that can occur on the IO line + */ + regmap_read(priv->regmap, offset, ®); + if (!(reg & TS4900_GPIO_OE)) { + if (value) + reg = TS4900_GPIO_OUT; + else + reg &= ~TS4900_GPIO_OUT; + + regmap_write(priv->regmap, offset, reg); + } + if (value) ret = regmap_write(priv->regmap, offset, TS4900_GPIO_OE | TS4900_GPIO_OUT); -- 2.11.0