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Date:   Mon, 07 Mar 2022 13:04:45 +0100
From:   Michael Walle <michael@walle.cc>
To:     Claudiu.Beznea@microchip.com
Cc:     Kavyasree.Kotagiri@microchip.com, Nicolas.Ferre@microchip.com,
        arnd@arndb.de, olof@lixom.net, soc@kernel.org,
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Subject: Re: [PATCH v1 3/6] ARM: dts: lan966x: add all flexcom usart nodes
In-Reply-To: <bf005cd2-4c83-1552-8282-d229eacc51f3@microchip.com>
References: <20220303160323.3316317-1-michael@walle.cc>
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 <a33f0c73-df49-5a22-14b3-0059f7d6b827@microchip.com>
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Am 2022-03-07 12:53, schrieb Claudiu.Beznea@microchip.com:
> On 04.03.2022 13:01, Michael Walle wrote:
>> EXTERNAL EMAIL: Do not click links or open attachments unless you know 
>> the
>> content is safe
>> 
>> Hi,
>> 
>> thanks for the quick review.
>> 
>> Am 2022-03-04 09:30, schrieb Claudiu.Beznea@microchip.com:
>>> On 03.03.2022 18:03, Michael Walle wrote:
>>>> EXTERNAL EMAIL: Do not click links or open attachments unless you 
>>>> know
>>>> the content is safe
>>>> 
>>>> Add all the usart nodes for the flexcom block. There was already
>>>> an usart node for the flexcom3 block. But it missed the DMA
>>>> channels.
>>> 
>>> And it would be good to go though a different patch.
>> 
>> sure
>> 
>>>> Although the DMA channels are specified, DMA is not
>>>> enabled by default because break detection doesn't work with DMA.
>>>> 
>>>> Keep the nodes disabled by default.
>>>> 
>>>> Signed-off-by: Michael Walle <michael@walle.cc>
>>>> ---
>>>>  arch/arm/boot/dts/lan966x.dtsi | 55
>>>> ++++++++++++++++++++++++++++++++++
>>>>  1 file changed, 55 insertions(+)
>>>> 
>>>> diff --git a/arch/arm/boot/dts/lan966x.dtsi
>>>> b/arch/arm/boot/dts/lan966x.dtsi
>>>> index a7d46a2ca058..bea69b6d2749 100644
>>>> --- a/arch/arm/boot/dts/lan966x.dtsi
>>>> +++ b/arch/arm/boot/dts/lan966x.dtsi
>>>> @@ -92,6 +92,19 @@ flx0: flexcom@e0040000 {
>>>>                         #size-cells = <1>;
>>>>                         ranges = <0x0 0xe0040000 0x800>;
>>>>                         status = "disabled";
>>>> +
>>>> +                       usart0: serial@200 {
>>>> +                               compatible =
>>>> "atmel,at91sam9260-usart";
>>> 
>>> Are the usart blocks in lan966x 1:1 compatible with what is is 
>>> sam9260?
>>> In
>>> case not it may worth to have a new compatible here, for lan966x, 
>>> such
>>> that
>>> when new features will be implemented in usart driver for lan966x the
>>> old
>>> DT (this one) will work with the new kernel implementation.
>> 
>> During my review of the inital dtsi patch, I've asked the same 
>> question
>> [1]
>> and I was told they are the same.
>> 
>> At least this exact usart compatible is already in this file. I was
>> under
>> the impression, that was the least controversial compatible :)
> 
> OK.
> 
>> 
>> But you'll need to tell me if they are the same or not, I don't have
>> any clue what microchip has reused.
> 
> From software point of view comparing registers should be good, as far 
> as I
> can tell. All AT91 datasheet should be available. I though you have 
> checked
> one against LAN966. At the moment I don't have a DS for LAN966. I'll 
> find
> one and have a look.

So my train of thought was like: even if the registers are the same I
cannot be sure that it is the exact same IP and will behave the same.
Therefore, it is something only microchip can answer.

You can find the registers at
https://microchip-ung.github.io/lan9668_reginfo/reginfo_LAN9668.html

I'm not aware of any "classic" datasheet.

-michael