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Mon, 7 Mar 2022 07:03:11 -0800 Received: from [10.216.32.253] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.15; Mon, 7 Mar 2022 07:03:05 -0800 Message-ID: <81e33d86-74f4-fead-a77e-aab5c2059996@quicinc.com> Date: Mon, 7 Mar 2022 20:33:01 +0530 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:91.0) Gecko/20100101 Thunderbird/91.3.2 Subject: Re: [PATCH] drm/msm/a6xx: Fix missing ARRAY_SIZE() check Content-Language: en-US To: Rob Clark , CC: , , "Rob Clark" , Dmitry Baryshkov , Sean Paul , Abhinav Kumar , David Airlie , Daniel Vetter , Jonathan Marek , Jordan Crouse , open list References: <20220305173405.914989-1-robdclark@gmail.com> From: Akhil P Oommen In-Reply-To: <20220305173405.914989-1-robdclark@gmail.com> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,NICE_REPLY_A,RCVD_IN_DNSWL_MED, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 3/5/2022 11:04 PM, Rob Clark wrote: > From: Rob Clark > > Fixes: f6d62d091cfd ("drm/msm/a6xx: add support for Adreno 660 GPU") > Signed-off-by: Rob Clark > Reviewed-by: Dmitry Baryshkov > --- > drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 12 ++++++++---- > 1 file changed, 8 insertions(+), 4 deletions(-) > > diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c > index 02b47977b5c3..83c31b2ad865 100644 > --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c > +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c > @@ -683,19 +683,23 @@ static void a6xx_set_cp_protect(struct msm_gpu *gpu) > { > struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); > const u32 *regs = a6xx_protect; > - unsigned i, count = ARRAY_SIZE(a6xx_protect), count_max = 32; > - > - BUILD_BUG_ON(ARRAY_SIZE(a6xx_protect) > 32); > - BUILD_BUG_ON(ARRAY_SIZE(a650_protect) > 48); > + unsigned i, count, count_max; > > if (adreno_is_a650(adreno_gpu)) { > regs = a650_protect; > count = ARRAY_SIZE(a650_protect); > count_max = 48; > + BUILD_BUG_ON(ARRAY_SIZE(a650_protect) > 48); > } else if (adreno_is_a660_family(adreno_gpu)) { > regs = a660_protect; > count = ARRAY_SIZE(a660_protect); > count_max = 48; > + BUILD_BUG_ON(ARRAY_SIZE(a660_protect) > 48); > + } else { > + regs = a6xx_protect; > + count = ARRAY_SIZE(a6xx_protect); > + count_max = 32; > + BUILD_BUG_ON(ARRAY_SIZE(a6xx_protect) > 32); > } > > /* Reviewed-by: Akhil P Oommen -Akhil.