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From:   Will Deacon <will@kernel.org>
To:     catalin.marinas@arm.com, Linu Cherian <lcherian@marvell.com>,
        maz@kernel.org, tglx@linutronix.de
Cc:     kernel-team@android.com, Will Deacon <will@kernel.org>,
        linuc.decode@gmail.com, linux-arm-kernel@lists.infradead.org,
        linux-kernel@vger.kernel.org
Subject: Re: [PATCH V3] irqchip/gic-v3: Workaround Marvell erratum 38545 when reading IAR
Date:   Mon,  7 Mar 2022 22:03:32 +0000
Message-Id: <164668950224.3277206.2552145973830842260.b4-ty@kernel.org>
In-Reply-To: <20220307143014.22758-1-lcherian@marvell.com>
References: <20220307143014.22758-1-lcherian@marvell.com>
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On Mon, 7 Mar 2022 20:00:14 +0530, Linu Cherian wrote:
> When a IAR register read races with a GIC interrupt RELEASE event,
> GIC-CPU interface could wrongly return a valid INTID to the CPU
> for an interrupt that is already released(non activated) instead of 0x3ff.
> 
> As a side effect, an interrupt handler could run twice, once with
> interrupt priority and then with idle priority.
> 
> [...]

Applied to arm64 (for-next/errata), thanks!

[1/1] irqchip/gic-v3: Workaround Marvell erratum 38545 when reading IAR
      https://git.kernel.org/arm64/c/24a147bcef8c

Cheers,
-- 
Will

https://fixes.arm64.dev
https://next.arm64.dev
https://will.arm64.dev