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From:   Vladimir Oltean <vladimir.oltean@nxp.com>
To:     Colin Foster <colin.foster@in-advantage.com>
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Subject: Re: [RFC v7 net-next 13/13] net: dsa: ocelot: add external ocelot
 switch control
Thread-Topic: [RFC v7 net-next 13/13] net: dsa: ocelot: add external ocelot
 switch control
Thread-Index: AQHYMcjV+C/Y5FAWfEOOeJZ/sjfXGqy1iiEA
Date:   Tue, 8 Mar 2022 14:14:40 +0000
Message-ID: <20220308141440.ggghkmkteey74cwo@skbuf>
References: <20220307021208.2406741-1-colin.foster@in-advantage.com>
 <20220307021208.2406741-14-colin.foster@in-advantage.com>
In-Reply-To: <20220307021208.2406741-14-colin.foster@in-advantage.com>
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On Sun, Mar 06, 2022 at 06:12:08PM -0800, Colin Foster wrote:
> +static const struct reg_field vsc7512_regfields[REGFIELD_MAX] =3D {
> +	[ANA_ADVLEARN_VLAN_CHK] =3D REG_FIELD(ANA_ADVLEARN, 11, 11),
> +	[ANA_ADVLEARN_LEARN_MIRROR] =3D REG_FIELD(ANA_ADVLEARN, 0, 10),
> +	[ANA_ANEVENTS_MSTI_DROP] =3D REG_FIELD(ANA_ANEVENTS, 27, 27),
> +	[ANA_ANEVENTS_ACLKILL] =3D REG_FIELD(ANA_ANEVENTS, 26, 26),
> +	[ANA_ANEVENTS_ACLUSED] =3D REG_FIELD(ANA_ANEVENTS, 25, 25),
> +	[ANA_ANEVENTS_AUTOAGE] =3D REG_FIELD(ANA_ANEVENTS, 24, 24),
> +	[ANA_ANEVENTS_VS2TTL1] =3D REG_FIELD(ANA_ANEVENTS, 23, 23),
> +	[ANA_ANEVENTS_STORM_DROP] =3D REG_FIELD(ANA_ANEVENTS, 22, 22),
> +	[ANA_ANEVENTS_LEARN_DROP] =3D REG_FIELD(ANA_ANEVENTS, 21, 21),
> +	[ANA_ANEVENTS_AGED_ENTRY] =3D REG_FIELD(ANA_ANEVENTS, 20, 20),
> +	[ANA_ANEVENTS_CPU_LEARN_FAILED] =3D REG_FIELD(ANA_ANEVENTS, 19, 19),
> +	[ANA_ANEVENTS_AUTO_LEARN_FAILED] =3D REG_FIELD(ANA_ANEVENTS, 18, 18),
> +	[ANA_ANEVENTS_LEARN_REMOVE] =3D REG_FIELD(ANA_ANEVENTS, 17, 17),
> +	[ANA_ANEVENTS_AUTO_LEARNED] =3D REG_FIELD(ANA_ANEVENTS, 16, 16),
> +	[ANA_ANEVENTS_AUTO_MOVED] =3D REG_FIELD(ANA_ANEVENTS, 15, 15),
> +	[ANA_ANEVENTS_DROPPED] =3D REG_FIELD(ANA_ANEVENTS, 14, 14),
> +	[ANA_ANEVENTS_CLASSIFIED_DROP] =3D REG_FIELD(ANA_ANEVENTS, 13, 13),
> +	[ANA_ANEVENTS_CLASSIFIED_COPY] =3D REG_FIELD(ANA_ANEVENTS, 12, 12),
> +	[ANA_ANEVENTS_VLAN_DISCARD] =3D REG_FIELD(ANA_ANEVENTS, 11, 11),
> +	[ANA_ANEVENTS_FWD_DISCARD] =3D REG_FIELD(ANA_ANEVENTS, 10, 10),
> +	[ANA_ANEVENTS_MULTICAST_FLOOD] =3D REG_FIELD(ANA_ANEVENTS, 9, 9),
> +	[ANA_ANEVENTS_UNICAST_FLOOD] =3D REG_FIELD(ANA_ANEVENTS, 8, 8),
> +	[ANA_ANEVENTS_DEST_KNOWN] =3D REG_FIELD(ANA_ANEVENTS, 7, 7),
> +	[ANA_ANEVENTS_BUCKET3_MATCH] =3D REG_FIELD(ANA_ANEVENTS, 6, 6),
> +	[ANA_ANEVENTS_BUCKET2_MATCH] =3D REG_FIELD(ANA_ANEVENTS, 5, 5),
> +	[ANA_ANEVENTS_BUCKET1_MATCH] =3D REG_FIELD(ANA_ANEVENTS, 4, 4),
> +	[ANA_ANEVENTS_BUCKET0_MATCH] =3D REG_FIELD(ANA_ANEVENTS, 3, 3),
> +	[ANA_ANEVENTS_CPU_OPERATION] =3D REG_FIELD(ANA_ANEVENTS, 2, 2),
> +	[ANA_ANEVENTS_DMAC_LOOKUP] =3D REG_FIELD(ANA_ANEVENTS, 1, 1),
> +	[ANA_ANEVENTS_SMAC_LOOKUP] =3D REG_FIELD(ANA_ANEVENTS, 0, 0),
> +	[ANA_TABLES_MACACCESS_B_DOM] =3D REG_FIELD(ANA_TABLES_MACACCESS, 18, 18=
),
> +	[ANA_TABLES_MACTINDX_BUCKET] =3D REG_FIELD(ANA_TABLES_MACTINDX, 10, 11)=
,
> +	[ANA_TABLES_MACTINDX_M_INDEX] =3D REG_FIELD(ANA_TABLES_MACTINDX, 0, 9),
> +	[GCB_SOFT_RST_SWC_RST] =3D REG_FIELD(GCB_SOFT_RST, 1, 1),

If you add GCB_SOFT_RST_SWC_RST to ocelot_regfields, can't you just use tha=
t?

> +	[QSYS_TIMED_FRAME_ENTRY_TFRM_VLD] =3D REG_FIELD(QSYS_TIMED_FRAME_ENTRY,=
 20, 20),
> +	[QSYS_TIMED_FRAME_ENTRY_TFRM_FP] =3D REG_FIELD(QSYS_TIMED_FRAME_ENTRY, =
8, 19),
> +	[QSYS_TIMED_FRAME_ENTRY_TFRM_PORTNO] =3D REG_FIELD(QSYS_TIMED_FRAME_ENT=
RY, 4, 7),
> +	[QSYS_TIMED_FRAME_ENTRY_TFRM_TM_SEL] =3D REG_FIELD(QSYS_TIMED_FRAME_ENT=
RY, 1, 3),
> +	[QSYS_TIMED_FRAME_ENTRY_TFRM_TM_T] =3D REG_FIELD(QSYS_TIMED_FRAME_ENTRY=
, 0, 0),
> +	[SYS_RESET_CFG_CORE_ENA] =3D REG_FIELD(SYS_RESET_CFG, 2, 2),
> +	[SYS_RESET_CFG_MEM_ENA] =3D REG_FIELD(SYS_RESET_CFG, 1, 1),
> +	[SYS_RESET_CFG_MEM_INIT] =3D REG_FIELD(SYS_RESET_CFG, 0, 0),
> +	/* Replicated per number of ports (12), register size 4 per port */
> +	[QSYS_SWITCH_PORT_MODE_PORT_ENA] =3D REG_FIELD_ID(QSYS_SWITCH_PORT_MODE=
, 14, 14, 12, 4),
> +	[QSYS_SWITCH_PORT_MODE_SCH_NEXT_CFG] =3D REG_FIELD_ID(QSYS_SWITCH_PORT_=
MODE, 11, 13, 12, 4),
> +	[QSYS_SWITCH_PORT_MODE_YEL_RSRVD] =3D REG_FIELD_ID(QSYS_SWITCH_PORT_MOD=
E, 10, 10, 12, 4),
> +	[QSYS_SWITCH_PORT_MODE_INGRESS_DROP_MODE] =3D REG_FIELD_ID(QSYS_SWITCH_=
PORT_MODE, 9, 9, 12, 4),
> +	[QSYS_SWITCH_PORT_MODE_TX_PFC_ENA] =3D REG_FIELD_ID(QSYS_SWITCH_PORT_MO=
DE, 1, 8, 12, 4),
> +	[QSYS_SWITCH_PORT_MODE_TX_PFC_MODE] =3D REG_FIELD_ID(QSYS_SWITCH_PORT_M=
ODE, 0, 0, 12, 4),
> +	[SYS_PORT_MODE_DATA_WO_TS] =3D REG_FIELD_ID(SYS_PORT_MODE, 5, 6, 12, 4)=
,
> +	[SYS_PORT_MODE_INCL_INJ_HDR] =3D REG_FIELD_ID(SYS_PORT_MODE, 3, 4, 12, =
4),
> +	[SYS_PORT_MODE_INCL_XTR_HDR] =3D REG_FIELD_ID(SYS_PORT_MODE, 1, 2, 12, =
4),
> +	[SYS_PORT_MODE_INCL_HDR_ERR] =3D REG_FIELD_ID(SYS_PORT_MODE, 0, 0, 12, =
4),
> +	[SYS_PAUSE_CFG_PAUSE_START] =3D REG_FIELD_ID(SYS_PAUSE_CFG, 10, 18, 12,=
 4),
> +	[SYS_PAUSE_CFG_PAUSE_STOP] =3D REG_FIELD_ID(SYS_PAUSE_CFG, 1, 9, 12, 4)=
,
> +	[SYS_PAUSE_CFG_PAUSE_ENA] =3D REG_FIELD_ID(SYS_PAUSE_CFG, 0, 1, 12, 4),
> +};
> +
> +static const struct ocelot_stat_layout vsc7512_stats_layout[] =3D {

Why not use ocelot_stats_layout?

> +	{ .offset =3D 0x00,	.name =3D "rx_octets", },
> +	{ .offset =3D 0x01,	.name =3D "rx_unicast", },
> +	{ .offset =3D 0x02,	.name =3D "rx_multicast", },
> +	{ .offset =3D 0x03,	.name =3D "rx_broadcast", },
> +	{ .offset =3D 0x04,	.name =3D "rx_shorts", },
> +	{ .offset =3D 0x05,	.name =3D "rx_fragments", },
> +	{ .offset =3D 0x06,	.name =3D "rx_jabbers", },
> +	{ .offset =3D 0x07,	.name =3D "rx_crc_align_errs", },
> +	{ .offset =3D 0x08,	.name =3D "rx_sym_errs", },
> +	{ .offset =3D 0x09,	.name =3D "rx_frames_below_65_octets", },
> +	{ .offset =3D 0x0A,	.name =3D "rx_frames_65_to_127_octets", },
> +	{ .offset =3D 0x0B,	.name =3D "rx_frames_128_to_255_octets", },
> +	{ .offset =3D 0x0C,	.name =3D "rx_frames_256_to_511_octets", },
> +	{ .offset =3D 0x0D,	.name =3D "rx_frames_512_to_1023_octets", },
> +	{ .offset =3D 0x0E,	.name =3D "rx_frames_1024_to_1526_octets", },
> +	{ .offset =3D 0x0F,	.name =3D "rx_frames_over_1526_octets", },
> +	{ .offset =3D 0x10,	.name =3D "rx_pause", },
> +	{ .offset =3D 0x11,	.name =3D "rx_control", },
> +	{ .offset =3D 0x12,	.name =3D "rx_longs", },
> +	{ .offset =3D 0x13,	.name =3D "rx_classified_drops", },
> +	{ .offset =3D 0x14,	.name =3D "rx_red_prio_0", },
> +	{ .offset =3D 0x15,	.name =3D "rx_red_prio_1", },
> +	{ .offset =3D 0x16,	.name =3D "rx_red_prio_2", },
> +	{ .offset =3D 0x17,	.name =3D "rx_red_prio_3", },
> +	{ .offset =3D 0x18,	.name =3D "rx_red_prio_4", },
> +	{ .offset =3D 0x19,	.name =3D "rx_red_prio_5", },
> +	{ .offset =3D 0x1A,	.name =3D "rx_red_prio_6", },
> +	{ .offset =3D 0x1B,	.name =3D "rx_red_prio_7", },
> +	{ .offset =3D 0x1C,	.name =3D "rx_yellow_prio_0", },
> +	{ .offset =3D 0x1D,	.name =3D "rx_yellow_prio_1", },
> +	{ .offset =3D 0x1E,	.name =3D "rx_yellow_prio_2", },
> +	{ .offset =3D 0x1F,	.name =3D "rx_yellow_prio_3", },
> +	{ .offset =3D 0x20,	.name =3D "rx_yellow_prio_4", },
> +	{ .offset =3D 0x21,	.name =3D "rx_yellow_prio_5", },
> +	{ .offset =3D 0x22,	.name =3D "rx_yellow_prio_6", },
> +	{ .offset =3D 0x23,	.name =3D "rx_yellow_prio_7", },
> +	{ .offset =3D 0x24,	.name =3D "rx_green_prio_0", },
> +	{ .offset =3D 0x25,	.name =3D "rx_green_prio_1", },
> +	{ .offset =3D 0x26,	.name =3D "rx_green_prio_2", },
> +	{ .offset =3D 0x27,	.name =3D "rx_green_prio_3", },
> +	{ .offset =3D 0x28,	.name =3D "rx_green_prio_4", },
> +	{ .offset =3D 0x29,	.name =3D "rx_green_prio_5", },
> +	{ .offset =3D 0x2A,	.name =3D "rx_green_prio_6", },
> +	{ .offset =3D 0x2B,	.name =3D "rx_green_prio_7", },
> +	{ .offset =3D 0x40,	.name =3D "tx_octets", },
> +	{ .offset =3D 0x41,	.name =3D "tx_unicast", },
> +	{ .offset =3D 0x42,	.name =3D "tx_multicast", },
> +	{ .offset =3D 0x43,	.name =3D "tx_broadcast", },
> +	{ .offset =3D 0x44,	.name =3D "tx_collision", },
> +	{ .offset =3D 0x45,	.name =3D "tx_drops", },
> +	{ .offset =3D 0x46,	.name =3D "tx_pause", },
> +	{ .offset =3D 0x47,	.name =3D "tx_frames_below_65_octets", },
> +	{ .offset =3D 0x48,	.name =3D "tx_frames_65_to_127_octets", },
> +	{ .offset =3D 0x49,	.name =3D "tx_frames_128_255_octets", },
> +	{ .offset =3D 0x4A,	.name =3D "tx_frames_256_511_octets", },
> +	{ .offset =3D 0x4B,	.name =3D "tx_frames_512_1023_octets", },
> +	{ .offset =3D 0x4C,	.name =3D "tx_frames_1024_1526_octets", },
> +	{ .offset =3D 0x4D,	.name =3D "tx_frames_over_1526_octets", },
> +	{ .offset =3D 0x4E,	.name =3D "tx_yellow_prio_0", },
> +	{ .offset =3D 0x4F,	.name =3D "tx_yellow_prio_1", },
> +	{ .offset =3D 0x50,	.name =3D "tx_yellow_prio_2", },
> +	{ .offset =3D 0x51,	.name =3D "tx_yellow_prio_3", },
> +	{ .offset =3D 0x52,	.name =3D "tx_yellow_prio_4", },
> +	{ .offset =3D 0x53,	.name =3D "tx_yellow_prio_5", },
> +	{ .offset =3D 0x54,	.name =3D "tx_yellow_prio_6", },
> +	{ .offset =3D 0x55,	.name =3D "tx_yellow_prio_7", },
> +	{ .offset =3D 0x56,	.name =3D "tx_green_prio_0", },
> +	{ .offset =3D 0x57,	.name =3D "tx_green_prio_1", },
> +	{ .offset =3D 0x58,	.name =3D "tx_green_prio_2", },
> +	{ .offset =3D 0x59,	.name =3D "tx_green_prio_3", },
> +	{ .offset =3D 0x5A,	.name =3D "tx_green_prio_4", },
> +	{ .offset =3D 0x5B,	.name =3D "tx_green_prio_5", },
> +	{ .offset =3D 0x5C,	.name =3D "tx_green_prio_6", },
> +	{ .offset =3D 0x5D,	.name =3D "tx_green_prio_7", },
> +	{ .offset =3D 0x5E,	.name =3D "tx_aged", },
> +	{ .offset =3D 0x80,	.name =3D "drop_local", },
> +	{ .offset =3D 0x81,	.name =3D "drop_tail", },
> +	{ .offset =3D 0x82,	.name =3D "drop_yellow_prio_0", },
> +	{ .offset =3D 0x83,	.name =3D "drop_yellow_prio_1", },
> +	{ .offset =3D 0x84,	.name =3D "drop_yellow_prio_2", },
> +	{ .offset =3D 0x85,	.name =3D "drop_yellow_prio_3", },
> +	{ .offset =3D 0x86,	.name =3D "drop_yellow_prio_4", },
> +	{ .offset =3D 0x87,	.name =3D "drop_yellow_prio_5", },
> +	{ .offset =3D 0x88,	.name =3D "drop_yellow_prio_6", },
> +	{ .offset =3D 0x89,	.name =3D "drop_yellow_prio_7", },
> +	{ .offset =3D 0x8A,	.name =3D "drop_green_prio_0", },
> +	{ .offset =3D 0x8B,	.name =3D "drop_green_prio_1", },
> +	{ .offset =3D 0x8C,	.name =3D "drop_green_prio_2", },
> +	{ .offset =3D 0x8D,	.name =3D "drop_green_prio_3", },
> +	{ .offset =3D 0x8E,	.name =3D "drop_green_prio_4", },
> +	{ .offset =3D 0x8F,	.name =3D "drop_green_prio_5", },
> +	{ .offset =3D 0x90,	.name =3D "drop_green_prio_6", },
> +	{ .offset =3D 0x91,	.name =3D "drop_green_prio_7", },
> +};
> +
> +static void ocelot_ext_phylink_validate(struct ocelot *ocelot, int port,
> +				     unsigned long *supported,
> +				     struct phylink_link_state *state)
> +{
> +	struct ocelot_port *ocelot_port =3D ocelot->ports[port];
> +
> +	__ETHTOOL_DECLARE_LINK_MODE_MASK(mask) =3D { 0, };
> +
> +	if (state->interface !=3D PHY_INTERFACE_MODE_NA &&
> +	    state->interface !=3D ocelot_port->phy_mode) {
> +		bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS);
> +		return;
> +	}

You might want to check
git log -4 --author=3D"Russell King" drivers/net/dsa/ocelot/
especially commit e57a15401e82 ("net: dsa: ocelot: remove interface checks"=
).
And you can/should in fact use phylink_generic_validate, since there
aren't any special constraints that I know of.

> +
> +	phylink_set_port_modes(mask);
> +
> +	phylink_set(mask, Pause);
> +	phylink_set(mask, Autoneg);
> +	phylink_set(mask, Asym_Pause);
> +	phylink_set(mask, 10baseT_Half);
> +	phylink_set(mask, 10baseT_Full);
> +	phylink_set(mask, 100baseT_Half);
> +	phylink_set(mask, 100baseT_Full);
> +	phylink_set(mask, 1000baseT_Half);
> +	phylink_set(mask, 1000baseT_Full);
> +
> +	bitmap_and(supported, supported, mask, __ETHTOOL_LINK_MODE_MASK_NBITS);
> +	bitmap_and(state->advertising, state->advertising, mask,
> +		   __ETHTOOL_LINK_MODE_MASK_NBITS);
> +}
> +
> +static struct vcap_props vsc7512_vcap_props[] =3D {

Why not vsc7514_vcap_props?

> +	[VCAP_ES0] =3D {
> +		.action_type_width =3D 0,
> +		.action_table =3D {
> +			[ES0_ACTION_TYPE_NORMAL] =3D {
> +				.width =3D 73,
> +				.count =3D 1,
> +			},
> +		},
> +		.target =3D S0,
> +		.keys =3D vsc7514_vcap_es0_keys,
> +		.actions =3D vsc7514_vcap_es0_actions,
> +	},
> +	[VCAP_IS1] =3D {
> +		.action_type_width =3D 0,
> +		.action_table =3D {
> +			[IS1_ACTION_TYPE_NORMAL] =3D {
> +				.width =3D 78,
> +				.count =3D 4,
> +			},
> +		},
> +		.target =3D S1,
> +		.keys =3D vsc7514_vcap_is1_keys,
> +		.actions =3D vsc7514_vcap_is1_actions,
> +	},
> +	[VCAP_IS2] =3D {
> +		.action_type_width =3D 1,
> +		.action_table =3D {
> +			[IS2_ACTION_TYPE_NORMAL] =3D {
> +				.width =3D 49,
> +				.count =3D 2,
> +			},
> +			[IS2_ACTION_TYPE_SMAC_SIP] =3D {
> +				.width =3D 6,
> +				.count =3D 4,
> +			},
> +		},
> +		.target =3D S2,
> +		.keys =3D vsc7514_vcap_is2_keys,
> +		.actions =3D vsc7514_vcap_is2_actions,
> +	},
> +};=