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d="scan'208";a="513267302" Received: from irsmsx605.ger.corp.intel.com ([163.33.146.138]) by orsmga006.jf.intel.com with ESMTP; 08 Mar 2022 13:06:27 -0800 Received: from orsmsx611.amr.corp.intel.com (10.22.229.24) by IRSMSX605.ger.corp.intel.com (163.33.146.138) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2308.21; Tue, 8 Mar 2022 21:06:26 +0000 Received: from orsmsx611.amr.corp.intel.com ([10.22.229.24]) by ORSMSX611.amr.corp.intel.com ([10.22.229.24]) with mapi id 15.01.2308.021; Tue, 8 Mar 2022 13:06:24 -0800 From: "Hall, Christopher S" To: "Hunter, Adrian" , Peter Zijlstra CC: Alexander Shishkin , "Arnaldo Carvalho de Melo" , Jiri Olsa , "linux-kernel@vger.kernel.org" , "Thomas Gleixner" , Ingo Molnar , "Borislav Petkov" , Dave Hansen , "x86@kernel.org" , "kvm@vger.kernel.org" , H Peter Anvin , Mathieu Poirier , Suzuki K Poulose , "Leo Yan" , "jgross@suse.com" , "sdeep@vmware.com" , "pv-drivers@vmware.com" , "pbonzini@redhat.com" , "seanjc@google.com" , "kys@microsoft.com" , "sthemmin@microsoft.com" , "virtualization@lists.linux-foundation.org" , "Andrew.Cooper3@citrix.com" Subject: RE: [PATCH V2 03/11] perf/x86: Add support for TSC in nanoseconds as a perf event clock Thread-Topic: [PATCH V2 03/11] perf/x86: Add support for TSC in nanoseconds as a perf event clock Thread-Index: AQHYMjGQwHF+1jrIb0imwpV8b7O+FKy2EdUA///IiFA= Date: Tue, 8 Mar 2022 21:06:24 +0000 Message-ID: <6f07a7d4e1ad4440bf6c502c8cb6c2ed@intel.com> References: <20220214110914.268126-1-adrian.hunter@intel.com> <20220214110914.268126-4-adrian.hunter@intel.com> <853ce127-25f0-d0fe-1d8f-0b0dd4f3ce71@intel.com> <30383f92-59cb-2875-1e1b-ff1a0eacd235@intel.com> <013b5425-2a60-e4d4-b846-444a576f2b28@intel.com> In-Reply-To: <013b5425-2a60-e4d4-b846-444a576f2b28@intel.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-product: dlpe-windows dlp-reaction: no-action dlp-version: 11.6.401.20 x-originating-ip: [10.22.254.132] Content-Type: text/plain; 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