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From:   nandhini.srikandan@intel.com
To:     fancer.lancer@gmail.com, broonie@kernel.org, robh+dt@kernel.org,
        linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org
Cc:     devicetree@vger.kernel.org, mgross@linux.intel.com,
        kris.pan@intel.com, kenchappa.demakkanavar@intel.com,
        furong.zhou@intel.com, mallikarjunappa.sangannavar@intel.com,
        mahesh.r.vaidya@intel.com, nandhini.srikandan@intel.com,
        rashmi.a@intel.com
Subject: [PATCH v4 0/3] Add support for Intel Thunder Bay SPI controller
Date:   Tue,  8 Mar 2022 18:33:28 +0800
Message-Id: <20220308103331.4116-1-nandhini.srikandan@intel.com>
Precedence: bulk

From: Nandhini Srikandan <nandhini.srikandan@intel.com>

Hi,

This patch enables support for DW SPI on Intel Thunder Bay (patch 1,2).
This patch set also enables master mode for latest Designware SPI versions (patch 3).

Patch 1: DW SPI DT bindings for Intel Thunder Bay SoC.
Patch 2: Adds support for Designware SPI on Intel Thunderbay SoC.
Patch 3: Adds master mode support for Designware SPI controller.

The driver is tested on Keem Bay and Thunder Bay evaluation board

Summary:
Changes from v3:
1) Dropped SSTE support in this patch.
2) Rebased to the latest code.

Changes from v2:
1) SSTE support made using dt and created seperate patches.
2) SPI controller master mode selection made common to all DW SPI controllers.
3) Using a common init function for both keem bay and thunder bay.

Changes from v1:
1) Designware CR0 specific macros are named in a generic way.
2) SPI CAP macros are named in generic way rather than naming project specific.
3) SPI KEEM BAY specific macros are replaced by generic macros.
4) Resued the existing SPI deassert API instead of adding another reset


Changes in patches:
Patch 1: 
Changes from v3/v2/v1:
1) No change in this patch

Patch 2:
Changes from v3:
1) No changes.

Changes from v2:
1) Init function is made common for Keem Bay and Thunder Bay.
 
Patch 3:
Changes from v3:
1) Corrected dw_spi_ip_is macro with the missing underscore.
2) Setting CTRLR0 BIT31 without any condition check as in older version of 
   DW SPI controller this bit is reserved.

Changes from v2/v1:
1)Newly introduced in v3 to make master mode selection as seperate patch

Thanks & Regards,
Nandhini


Nandhini Srikandan (3):
  dt-bindings: spi: Add bindings for Intel Thunder Bay SoC
  spi: dw: Add support for Intel Thunder Bay SPI controller
  spi: dw: Add support for master mode selection for DWC SSI controller

 .../devicetree/bindings/spi/snps,dw-apb-ssi.yaml          | 2 ++
 drivers/spi/spi-dw-core.c                                 | 4 ++--
 drivers/spi/spi-dw-mmio.c                                 | 8 ++++----
 drivers/spi/spi-dw.h                                      | 7 +++----
 4 files changed, 11 insertions(+), 10 deletions(-)

-- 
2.17.1