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[2620:137:e000::1:18]) by mx.google.com with ESMTPS id d83-20020a621d56000000b004f41abe3900si285310pfd.273.2022.03.08.16.13.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 08 Mar 2022 16:13:22 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:18 as permitted sender) client-ip=2620:137:e000::1:18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 1F0C5F392E; Tue, 8 Mar 2022 15:42:12 -0800 (PST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1348668AbiCHRsR (ORCPT + 99 others); Tue, 8 Mar 2022 12:48:17 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37976 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232292AbiCHRsQ (ORCPT ); Tue, 8 Mar 2022 12:48:16 -0500 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id E5998554A5 for ; Tue, 8 Mar 2022 09:47:19 -0800 (PST) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id A6E7E139F; Tue, 8 Mar 2022 09:47:19 -0800 (PST) Received: from [10.57.41.254] (unknown [10.57.41.254]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 6A2293FA45; Tue, 8 Mar 2022 09:47:17 -0800 (PST) Message-ID: <8336bc6e-0f11-9cfe-b513-b30858d01cc6@arm.com> Date: Tue, 8 Mar 2022 17:47:12 +0000 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; rv:91.0) Gecko/20100101 Thunderbird/91.6.2 Subject: Re: [PATCH RFC] arm64: improve display about CPU architecture in cpuinfo Content-Language: en-GB To: Catalin Marinas Cc: Arnd Bergmann , Marc Zyngier , Rongwei Wang , Will Deacon , joey.gouly@arm.com, Mark Rutland , Andrew Morton , Linux ARM , Linux Kernel Mailing List References: <20220307030417.22974-1-rongwei.wang@linux.alibaba.com> <87h78a178u.wl-maz@kernel.org> <87bkyi0x53.wl-maz@kernel.org> <1b94af8b-a294-5765-4e1e-896f70db621f@arm.com> <9296f97c-f894-001c-53e6-41bbfe36ce71@arm.com> From: Robin Murphy In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,NICE_REPLY_A, RDNS_NONE,SPF_HELO_NONE,T_SCC_BODY_TEXT_LINE autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 2022-03-08 17:18, Catalin Marinas wrote: > On Mon, Mar 07, 2022 at 08:05:06PM +0000, Robin Murphy wrote: >> On 2022-03-07 19:30, Arnd Bergmann wrote: >>> On Mon, Mar 7, 2022 at 5:48 PM Robin Murphy wrote: >>> >>>> And arguably it's not even too late, because 10 years ago this *did* say >>>> "AArch64". I don't remember all the exact details behind commit >>>> 44b82b7700d0 ("arm64: Fix up /proc/cpuinfo") - this just tickled enough >>>> of a memory to go and look up the git history - but I don't think we >>>> changed any of those fields without a real reason. >>>> >>> >>> The patch description does state that this was done for compatibility with >>> 32-bit architectures, which does make some sense. I suppose for similar >>> reasons, the arch/arm/ version of /proc/cpuinfo is now stuck at >>> 'CPU architecture: 7', even for ARMv8 or higher in aarch32 mode. >>> >>> The part that I find more annoying is how we leave out the one bit >>> of information that people are generally looking for in /proc/cpuinfo: >>> the name of the processor. Even though we already know the >>> exact processor type in order to handle the CPU errata, this is >>> always "model name\t: ARMv7 Processor rev %d (v7l)" on 32-bit, >>> and "model name\t: ARMv8 Processor rev %d (%s)" on 64-bit, >>> with the revision being the least important bit of information here... >> >> Eh, it's hardly impossible to recompose a MIDR value from the implementer, >> part, variant and revision fields if one actually needs to. Maybe we could >> null-terminate the raw MIDR value and print it as a string of >> largely-unprintable characters in the "model name" field... I guess that >> might satisfy the crowd who want parity* with x86 CPUID, at least :) > > You can get the MIDR from > /sys/devices/system/cpu/cpu*/regs/identification/midr_el1. > > As for printing the actual names, we thought we'd leave it to tools like > lscpu. I'm not keen on maintaining a dictionary of MIDR to CPU marketing > names in the kernel, deal with rebranding and so on. For x86 you can get > the name from the CPU itself IIUC, that's not the case for arm. Yes, CPUID reads a string out of the hardware which is the name for the *physical product*, which among other things is allegedly useful to dissuade unscrupulous people from grinding the markings off and re-etching them to fake a higher-spec chip. We obviously can't maintain a whole database of SoC names in Linux. In fact on my x86 box, even lscpu still doesn't tell me what the actual CPU cores are other than family 6 model 79, so in that respect Arm support is already ahead! :D Robin.