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From:   Vladimir Oltean <vladimir.oltean@nxp.com>
To:     Colin Foster <colin.foster@in-advantage.com>
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Subject: Re: [RFC v7 net-next 10/13] mfd: ocelot: add support for the vsc7512
 chip via spi
Thread-Topic: [RFC v7 net-next 10/13] mfd: ocelot: add support for the vsc7512
 chip via spi
Thread-Index: AQHYMcjTRgIrF6Xyik+JLHWvUw480qy1kJUA
Date:   Tue, 8 Mar 2022 14:37:47 +0000
Message-ID: <20220308143746.w5ccuk3mvzdzno2x@skbuf>
References: <20220307021208.2406741-1-colin.foster@in-advantage.com>
 <20220307021208.2406741-11-colin.foster@in-advantage.com>
In-Reply-To: <20220307021208.2406741-11-colin.foster@in-advantage.com>
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On Sun, Mar 06, 2022 at 06:12:05PM -0800, Colin Foster wrote:
> The VSC7512 is a networking chip that contains several peripherals. Many =
of
> these peripherals are currently supported by the VSC7513 and VSC7514 chip=
s,
> but those run on an internal CPU. The VSC7512 lacks this CPU, and must be
> controlled externally.
>=20
> Utilize the existing drivers by referencing the chip as an MFD. Add suppo=
rt
> for the two MDIO buses, the internal phys, pinctrl, serial GPIO, and HSIO=
.
>=20
> Signed-off-by: Colin Foster <colin.foster@in-advantage.com>
> ---
> +#define VSC7512_MIIM0_RES_START	0x7107009c
> +#define VSC7512_MIIM0_RES_SIZE	0x24
> +
> +#define VSC7512_MIIM1_RES_START	0x710700c0
> +#define VSC7512_MIIM1_RES_SIZE	0x24
> +
> +#define VSC7512_PHY_RES_START	0x710700f0
> +#define VSC7512_PHY_RES_SIZE	0x4
> +
> +#define VSC7512_HSIO_RES_START	0x710d0000
> +#define VSC7512_HSIO_RES_SIZE	0x10000
> +
> +#define VSC7512_GPIO_RES_START	0x71070034
> +#define VSC7512_GPIO_RES_SIZE	0x6c
> +
> +#define VSC7512_SIO_RES_START	0x710700f8
> +#define VSC7512_SIO_RES_SIZE	0x100
> +
> +static const struct resource vsc7512_gcb_resource =3D
> +	DEFINE_RES_REG_NAMED(VSC7512_GCB_RES_START, VSC7512_GCB_RES_SIZE,
> +			     "devcpu_gcb_chip_regs");
> +static const struct resource vsc7512_miim0_resources[] =3D {
> +	DEFINE_RES_REG_NAMED(VSC7512_MIIM0_RES_START, VSC7512_MIIM0_RES_SIZE,
> +			     "gcb_miim0"),
> +	DEFINE_RES_REG_NAMED(VSC7512_PHY_RES_START, VSC7512_PHY_RES_SIZE,
> +			     "gcb_phy"),
> +};
> +
> +static const struct resource vsc7512_miim1_resources[] =3D {
> +	DEFINE_RES_REG_NAMED(VSC7512_MIIM1_RES_START, VSC7512_MIIM1_RES_SIZE,
> +			     "gcb_miim1"),
> +};
> +
> +static const struct resource vsc7512_hsio_resources[] =3D {
> +	DEFINE_RES_REG_NAMED(VSC7512_HSIO_RES_START, VSC7512_HSIO_RES_SIZE,
> +			     "hsio"),
> +};
> +
> +static const struct resource vsc7512_pinctrl_resources[] =3D {
> +	DEFINE_RES_REG_NAMED(VSC7512_GPIO_RES_START, VSC7512_GPIO_RES_SIZE,
> +			     "gcb_gpio"),
> +};
> +
> +static const struct resource vsc7512_sgpio_resources[] =3D {
> +	DEFINE_RES_REG_NAMED(VSC7512_SIO_RES_START, VSC7512_SIO_RES_SIZE,
> +			     "gcb_sio"),
> +};
> +
> +static const struct mfd_cell vsc7512_devs[] =3D {
> +	{
> +		.name =3D "ocelot-pinctrl",
> +		.of_compatible =3D "mscc,ocelot-pinctrl",
> +		.num_resources =3D ARRAY_SIZE(vsc7512_pinctrl_resources),
> +		.resources =3D vsc7512_pinctrl_resources,
> +	}, {
> +		.name =3D "ocelot-sgpio",
> +		.of_compatible =3D "mscc,ocelot-sgpio",
> +		.num_resources =3D ARRAY_SIZE(vsc7512_sgpio_resources),
> +		.resources =3D vsc7512_sgpio_resources,
> +	}, {
> +		.name =3D "ocelot-miim0",
> +		.of_compatible =3D "mscc,ocelot-miim",
> +		.num_resources =3D ARRAY_SIZE(vsc7512_miim0_resources),
> +		.resources =3D vsc7512_miim0_resources,
> +	}, {
> +		.name =3D "ocelot-miim1",
> +		.of_compatible =3D "mscc,ocelot-miim",
> +		.num_resources =3D ARRAY_SIZE(vsc7512_miim1_resources),
> +		.resources =3D vsc7512_miim1_resources,

I'm looking at mfd_match_of_node_to_dev() and I don't really understand
how the first MDIO bus matches the first mfd_cell's resources, and the
second MDIO bus the second mfd_cell? By order of definition?

> +	}, {
> +		.name =3D "ocelot-serdes",
> +		.of_compatible =3D "mscc,vsc7514-serdes",
> +		.num_resources =3D ARRAY_SIZE(vsc7512_hsio_resources),
> +		.resources =3D vsc7512_hsio_resources,
> +	},
> +};
> +
> +int ocelot_core_init(struct ocelot_core *core)
> +{
> +	struct device *dev =3D core->dev;
> +	int ret;
> +
> +	dev_set_drvdata(dev, core);
> +
> +	core->gcb_regmap =3D ocelot_devm_regmap_init(core, dev,
> +						   &vsc7512_gcb_resource);
> +	if (IS_ERR(core->gcb_regmap))
> +		return -ENOMEM;
> +
> +	ret =3D ocelot_reset(core);
> +	if (ret) {
> +		dev_err(dev, "Failed to reset device: %d\n", ret);
> +		return ret;
> +	}
> +
> +	/*
> +	 * A chip reset will clear the SPI configuration, so it needs to be don=
e
> +	 * again before we can access any registers
> +	 */
> +	ret =3D ocelot_spi_initialize(core);
> +	if (ret) {
> +		dev_err(dev, "Failed to initialize SPI interface: %d\n", ret);
> +		return ret;
> +	}
> +
> +	ret =3D devm_mfd_add_devices(dev, PLATFORM_DEVID_AUTO, vsc7512_devs,
> +				   ARRAY_SIZE(vsc7512_devs), NULL, 0, NULL);
> +	if (ret) {
> +		dev_err(dev, "Failed to add sub-devices: %d\n", ret);
> +		return ret;
> +	}
> +
> +	return 0;
> +}
> +EXPORT_SYMBOL(ocelot_core_init);
> --=20
> 2.25.1
>=