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X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Mar 2022 12:00:34.9230 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 99e6a699-0c3d-4789-2300-08da01c46b32 X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c;Ip=[149.199.62.198];Helo=[xsj-pvapexch01.xlnx.xilinx.com] X-MS-Exchange-CrossTenant-AuthSource: SN1NAM02FT0033.eop-nam02.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA2PR02MB7562 X-Spam-Status: No, score=1.1 required=5.0 tests=AC_FROM_MANY_DOTS,BAYES_00, DKIM_SIGNED,DKIM_VALID,RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H2, SPF_HELO_PASS,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=no autolearn_force=no version=3.4.6 X-Spam-Level: * X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Xilinx Versal Premium series has CPM5 block which supports Root Port functioning at Gen5 speed. Xilinx Versal CPM5 has few changes with existing CPM block. - CPM5 has dedicated register space for control and status registers. - CPM5 legacy interrupt handling needs additonal register bit to enable and handle legacy interrupts. Changes in v3: - consistency in is_cpm5 flag check expression. Bharat Kumar Gogada (2): dt-bindings: PCI: xilinx-cpm: Add Versal CPM5 Root Port PCI: xilinx-cpm: Add support for Versal CPM5 Root Port .../bindings/pci/xilinx-versal-cpm.yaml | 47 ++++++++++++++++--- drivers/pci/controller/pcie-xilinx-cpm.c | 33 ++++++++++++- 2 files changed, 72 insertions(+), 8 deletions(-) -- 2.17.1