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Wed, 9 Mar 2022 11:58:19 -0600 From: Alex Deucher To: , , , , , , , , , , , , , CC: Alex Deucher Subject: [PATCH v2 1/2] Documentation: x86: Add documenation for AMD IOMMU Date: Wed, 9 Mar 2022 12:58:04 -0500 Message-ID: <20220309175805.1298503-1-alexander.deucher@amd.com> X-Mailer: git-send-email 2.35.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: c8793688-748d-46ec-9908-08da01f66727 X-MS-TrafficTypeDiagnostic: CY4PR12MB1285:EE_ X-Microsoft-Antispam-PRVS: X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: JYz0V7siruAQ8BxGCfv8X3oYruBtnsWLBOnMfIQxHey5cOQBEp/Gvz+HpJ7HlSpbJeFZvpqF/sSUZoR48ZcyEZttoj5GbR79DJADCmivhHMA66NbRwskcDnY3F0mMHKae4Oz8VCJqQ2RQ3k1d4zk5FbYa05gqx7yBViktVXFosiEC6XTji321rNny+mTOzeQBoOzRi5D/qabhGMMRTFY0b0G3Re/YW0HzLQ7I5e9R+CSZPkNw1YBFRlOOiFL94rHacda1mz0/fSSbYk3nZZO0t8G2SRSOfNwGmXi99hqDW7c6mndCh9n9ribUccrbiO8owiNaCMUHXSftZa19h43Konjxe6oONO+swqwlQtiYul/WoKlix3x/7Eq17bfdbh/CeH9Ba+hYW3cYUcqIyhvfOSJqdfg/L+REgN+TjUBpogvClOyTzZbJt8Fd0/WGTtj/zw7XiEoLv3aIXcRaQmhaxPIYL5ZnJqdU5R5GeaGVQPFvL3UC0gIRIF8LzVVbeHm/9As3Vuz7oM/YBIKaO+lBxmcdj/p63lGKgFz0joj8LaD7MLhI8DQZ3j6gO95QhnOVnJqI2KSYZBL6cnxW81tmhkqTYL4qrUcDUDrce0L+QS3GAm4x6AJya67Qp7TChEKtFZjOKy1C/hRrAFh/lp3B3FrciSxEB19ZtXoidJ2jZCJvEK9Qc+OIttfvjBF7UyJCWQvPwrbVtdrv3VLLYq+DoNGEvfh7laiQx7XlyBRhjRechqjZU5LwTOjqwPJXa6FzNlO4IDfZwfKjJmRfWedvi0355fU2RqK0pg43vMchE6pwm288HZSX7Y8eZGSW54u X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230001)(4636009)(36840700001)(46966006)(40470700004)(336012)(40460700003)(426003)(110136005)(47076005)(6666004)(70586007)(70206006)(36860700001)(36756003)(4326008)(8676002)(7696005)(2616005)(1076003)(86362001)(16526019)(5660300002)(7416002)(82310400004)(2906002)(508600001)(83380400001)(921005)(8936002)(81166007)(356005)(186003)(26005)(316002)(36900700001);DIR:OUT;SFP:1101; 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Signed-off-by: Alex Deucher --- V2: incorporate feedback from Robin to clarify IOMMU vs DMA engine (e.g., a device) and document proper DMA API. Also correct the fact that the AMD IOMMU is not limited to managing PCI devices. Documentation/x86/amd-iommu.rst | 69 +++++++++++++++++++++++++++++++ Documentation/x86/index.rst | 1 + Documentation/x86/intel-iommu.rst | 2 +- 3 files changed, 71 insertions(+), 1 deletion(-) create mode 100644 Documentation/x86/amd-iommu.rst diff --git a/Documentation/x86/amd-iommu.rst b/Documentation/x86/amd-iommu.rst new file mode 100644 index 000000000000..6ecc4bc8c70d --- /dev/null +++ b/Documentation/x86/amd-iommu.rst @@ -0,0 +1,69 @@ +================= +AMD IOMMU Support +================= + +The architecture spec can be obtained from the below location. + +https://www.amd.com/system/files/TechDocs/48882_IOMMU.pdf + +This guide gives a quick cheat sheet for some basic understanding. + +Some Keywords + +- IVRS - I/O Virtualization Reporting Structure +- IVDB - I/O Virtualization Definition Block +- IVHD - I/O Virtualization Hardware Definition +- IOVA - I/O Virtual Address. + +Basic stuff +----------- + +ACPI enumerates and lists the different IOMMUs on the platform, and +device scope relationships between devices and which IOMMU controls +them. + +What is IVRS? +------------- + +The architecture defines an ACPI-compatible data structure called an I/O +Virtualization Reporting Structure (IVRS) that is used to convey information +related to I/O virtualization to system software. The IVRS describes the +configuration and capabilities of the IOMMUs contained in the platform as +well as information about the devices that each IOMMU virtualizes. + +The IVRS provides information about the following: +- IOMMUs present in the platform including their capabilities and proper configuration +- System I/O topology relevant to each IOMMU +- Peripheral devices that cannot be otherwise enumerated +- Memory regions used by SMI/SMM, platform firmware, and platform hardware. These are +generally exclusion ranges to be configured by system software. + +How is IOVA generated? +---------------------- + +Well behaved drivers call dma_map_*() calls before sending command to device +that needs to perform DMA. Once DMA is completed and mapping is no longer +required, driver performs dma_unmap_*() calls to unmap the region. + +Fault reporting +--------------- + +When errors are reported, the IOMMU signals via an interrupt. The fault +reason and device that caused it with fault reason is printed on console. + +Boot Message Sample +------------------- + +Something like this gets printed indicating presence of the IOMMU. + + iommu: Default domain type: Translated + iommu: DMA domain TLB invalidation policy: lazy mode + +Fault reporting +^^^^^^^^^^^^^^^ + +:: + + AMD-Vi: Event logged [IO_PAGE_FAULT domain=0x0007 address=0xffffc02000 flags=0x0000] + AMD-Vi: Event logged [IO_PAGE_FAULT device=07:00.0 domain=0x0007 address=0xffffc02000 flags=0x0000] + diff --git a/Documentation/x86/index.rst b/Documentation/x86/index.rst index f498f1d36cd3..15711134eb68 100644 --- a/Documentation/x86/index.rst +++ b/Documentation/x86/index.rst @@ -22,6 +22,7 @@ x86-specific Documentation mtrr pat intel-iommu + amd-iommu intel_txt amd-memory-encryption pti diff --git a/Documentation/x86/intel-iommu.rst b/Documentation/x86/intel-iommu.rst index 099f13d51d5f..4d3391c7bd3f 100644 --- a/Documentation/x86/intel-iommu.rst +++ b/Documentation/x86/intel-iommu.rst @@ -1,5 +1,5 @@ =================== -Linux IOMMU Support +Intel IOMMU Support =================== The architecture spec can be obtained from the below location. -- 2.35.1