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Wed, 9 Mar 2022 11:58:20 -0600 From: Alex Deucher To: , , , , , , , , , , , , , CC: Alex Deucher Subject: [PATCH 2/2] Documentation: x86: Clarify Intel IOMMU documenation Date: Wed, 9 Mar 2022 12:58:05 -0500 Message-ID: <20220309175805.1298503-2-alexander.deucher@amd.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220309175805.1298503-1-alexander.deucher@amd.com> References: <20220309175805.1298503-1-alexander.deucher@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: ac905de1-f8e1-47b0-07fa-08da01f6679a X-MS-TrafficTypeDiagnostic: MWHPR12MB1694:EE_ X-Microsoft-Antispam-PRVS: X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 4fvUd24HY5pwqhPuIOWl1OVtU5oX7VkLCAHGOzvT244HZWW2RkZAre0Kp2BQvcLjbxSYNzsDz1784GVHHT7+8sKJKJ7L2FZoiAv6AaTKna1GiUrhePRF3A87jqeIIRhrjJkcMcHAint9IYHDPThUoAYAkhBHzdWK2XmJYXGcZyk5Jwl56Y1ZWo+nM7H/83WtcdmwALT/ooL9fbkNU8Q7YBXO4PT2AZXoI8iJH9JRRg7MDdmYh3np4gU8N6va3dZdVj9QvSvBvSn970r4xTZNAWBFdl8K82Lcsh8ALcDBA+oAITwGtDMFvYmilTLxhvqzzH5JhUW0JuvB5jKWoe0g/DhaUmhuIkIi9MkhnmkYRZm/XHss0u32WIIRGemSwINzWae42dPuvzs4tTHOOYddnaYWOWGAdbL82yr5Z0ZyF7DF/dDfEV67IP/e6GVAtLixt113MWR4vFkhUi9tGPXSSFhfVYlSiXuEMxCvRjdYnHiWYVcrRkwXVI8ouYn/dusuoSVHltHbFRFKLAjRZ3bcQwkN3jEsL8DaafWwhDAC9NDBp48+4KYLu7XPQEZww9i2MbR0G7qoWupjZb04Ysg4oVL/V7hAO4x6Ez+wJy20qyIkQNBjFlxwb5F5BS9qxHZSqAjkTf7hnaaGoq1rGn1uMMpYWUa5Dj5e1Qii96uVJzXN2evS0qT2vgskaKc78+rkPVzcjmB5zgivvyjzahqPheQQzdI5F3BF91BlGK/Q8GU= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230001)(4636009)(36840700001)(46966006)(40470700004)(921005)(8676002)(70586007)(70206006)(86362001)(4326008)(82310400004)(7416002)(83380400001)(40460700003)(2906002)(356005)(16526019)(426003)(81166007)(36860700001)(8936002)(2616005)(1076003)(6666004)(186003)(336012)(36756003)(26005)(7696005)(316002)(110136005)(508600001)(47076005)(5660300002)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Mar 2022 17:58:23.7139 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ac905de1-f8e1-47b0-07fa-08da01f6679a X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT063.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MWHPR12MB1694 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Based on feedback from Robin on the initial AMD IOMMU documentation, fix up the Intel documentation to clarify IOMMU vs device and modern DMA API. Signed-off-by: Alex Deucher --- Documentation/x86/intel-iommu.rst | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/Documentation/x86/intel-iommu.rst b/Documentation/x86/intel-iommu.rst index 4d3391c7bd3f..22e1934a1335 100644 --- a/Documentation/x86/intel-iommu.rst +++ b/Documentation/x86/intel-iommu.rst @@ -19,8 +19,8 @@ Some Keywords Basic stuff ----------- -ACPI enumerates and lists the different DMA engines in the platform, and -device scope relationships between PCI devices and which DMA engine controls +ACPI enumerates and lists the different IOMMUs in the platform, and +device scope relationships between PCI devices and which IOMMU controls them. What is RMRR? @@ -36,9 +36,9 @@ unity mappings for these regions for these devices to access these regions. How is IOVA generated? ---------------------- -Well behaved drivers call pci_map_*() calls before sending command to device +Well behaved drivers call dma_map_*() calls before sending command to device that needs to perform DMA. Once DMA is completed and mapping is no longer -required, device performs a pci_unmap_*() calls to unmap the region. +required, device performs a dma_unmap_*() calls to unmap the region. The Intel IOMMU driver allocates a virtual address per domain. Each PCIE device has its own domain (hence protection). Devices under p2p bridges @@ -68,7 +68,7 @@ address from PCI MMIO ranges so they are not allocated for IOVA addresses. Fault reporting --------------- -When errors are reported, the DMA engine signals via an interrupt. The fault +When errors are reported, the IOMMU signals via an interrupt. The fault reason and device that caused it with fault reason is printed on console. See below for sample. -- 2.35.1