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Received: from DM6PR12MB2906.namprd12.prod.outlook.com (2603:10b6:5:15f::20) by SJ0PR12MB5455.namprd12.prod.outlook.com (2603:10b6:a03:3ba::12) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5038.14; Thu, 10 Mar 2022 04:17:51 +0000 Received: from DM6PR12MB2906.namprd12.prod.outlook.com ([fe80::3933:c8b5:f45:f848]) by DM6PR12MB2906.namprd12.prod.outlook.com ([fe80::3933:c8b5:f45:f848%2]) with mapi id 15.20.5038.027; Thu, 10 Mar 2022 04:17:51 +0000 Message-ID: <6e63dd2b-de01-c707-cf4b-33eb7d1eb0c4@amd.com> Date: Thu, 10 Mar 2022 09:47:36 +0530 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:91.0) Gecko/20100101 Thunderbird/91.4.0 Subject: Re: [PATCH v2 1/2] Documentation: x86: Add documenation for AMD IOMMU Content-Language: en-US To: Alex Deucher , linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, corbet@lwn.net, hpa@zytor.com, x86@kernel.org, dave.hansen@linux.intel.com, bp@alien8.de, mingo@redhat.com, tglx@linutronix.de, joro@8bytes.org, suravee.suthikulpanit@amd.com, will@kernel.org, iommu@lists.linux-foundation.org, robin.murphy@arm.com References: <20220309175805.1298503-1-alexander.deucher@amd.com> From: Vasant Hegde In-Reply-To: <20220309175805.1298503-1-alexander.deucher@amd.com> Content-Type: text/plain; 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Also correct the fact that > the AMD IOMMU is not limited to managing PCI devices. > > Documentation/x86/amd-iommu.rst | 69 +++++++++++++++++++++++++++++++ > Documentation/x86/index.rst | 1 + > Documentation/x86/intel-iommu.rst | 2 +- > 3 files changed, 71 insertions(+), 1 deletion(-) > create mode 100644 Documentation/x86/amd-iommu.rst > > diff --git a/Documentation/x86/amd-iommu.rst b/Documentation/x86/amd-iommu.rst > new file mode 100644 > index 000000000000..6ecc4bc8c70d > --- /dev/null > +++ b/Documentation/x86/amd-iommu.rst > @@ -0,0 +1,69 @@ > +================= > +AMD IOMMU Support > +================= > + > +The architecture spec can be obtained from the below location. > + > +https://www.amd.com/system/files/TechDocs/48882_IOMMU.pdf > + > +This guide gives a quick cheat sheet for some basic understanding. > + > +Some Keywords > + > +- IVRS - I/O Virtualization Reporting Structure > +- IVDB - I/O Virtualization Definition Block > +- IVHD - I/O Virtualization Hardware Definition > +- IOVA - I/O Virtual Address. > + > +Basic stuff > +----------- > + > +ACPI enumerates and lists the different IOMMUs on the platform, and > +device scope relationships between devices and which IOMMU controls > +them. > + > +What is IVRS? > +------------- > + > +The architecture defines an ACPI-compatible data structure called an I/O > +Virtualization Reporting Structure (IVRS) that is used to convey information > +related to I/O virtualization to system software. The IVRS describes the > +configuration and capabilities of the IOMMUs contained in the platform as > +well as information about the devices that each IOMMU virtualizes. > + > +The IVRS provides information about the following: > +- IOMMUs present in the platform including their capabilities and proper configuration > +- System I/O topology relevant to each IOMMU > +- Peripheral devices that cannot be otherwise enumerated > +- Memory regions used by SMI/SMM, platform firmware, and platform hardware. These are > +generally exclusion ranges to be configured by system software. > + > +How is IOVA generated? > +---------------------- > + > +Well behaved drivers call dma_map_*() calls before sending command to device > +that needs to perform DMA. Once DMA is completed and mapping is no longer > +required, driver performs dma_unmap_*() calls to unmap the region. > + > +Fault reporting > +--------------- > + > +When errors are reported, the IOMMU signals via an interrupt. The fault > +reason and device that caused it with fault reason is printed on console. May be just say "... and device cause it is printed on console."? Rest looks good to me. -Vasant