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Subject: Re: [PATCH v1 2/7] clk: starfive: jh7100: Handle audio_div clock properly
From:   Stephen Boyd <sboyd@kernel.org>
Cc:     Emil Renner Berthing <kernel@esmil.dk>,
        Michael Turquette <mturquette@baylibre.com>,
        Rob Herring <robh+dt@kernel.org>,
        Andy Shevchenko <andy.shevchenko@gmail.com>,
        Geert Uytterhoeven <geert@linux-m68k.org>,
        Arnd Bergmann <arnd@arndb.de>,
        Michael Zhu <michael.zhu@starfivetech.com>,
        Fu Wei <tekkamanninja@gmail.com>, linux-kernel@vger.kernel.org
To:     Emil Renner Berthing <kernel@esmil.dk>, devicetree@vger.kernel.org,
        linux-clk@vger.kernel.org
Date:   Thu, 10 Mar 2022 18:53:38 -0800
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Quoting Emil Renner Berthing (2022-01-26 09:39:48)
> It turns out the audio_div clock is a fractional divider where the
> lowest byte of the ctrl register is the integer part of the divider and
> the 2nd byte is the number of 100th added to the divider.
>=20
> The children of this clock is used by the audio peripherals for their
> sample rate clock, so round to the closest possible rate rather than
> always rounding down like regular dividers.
>=20
> Fixes: 4210be668a09 ("clk: starfive: Add JH7100 clock generator driver")
> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
> ---

Applied to clk-next