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From:   "Hawkins, Nick" <nick.hawkins@hpe.com>
To:     Rob Herring <robh@kernel.org>
CC:     "Verdun, Jean-Marie" <verdun@hpe.com>,
        Daniel Lezcano <daniel.lezcano@linaro.org>,
        Thomas Gleixner <tglx@linutronix.de>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
        "devicetree@vger.kernel.org" <devicetree@vger.kernel.org>
Subject: RE: [PATCH v3 05/10] dt-bindings: timer: Add HPE GXP Timer Binding
Thread-Topic: [PATCH v3 05/10] dt-bindings: timer: Add HPE GXP Timer Binding
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Date:   Fri, 11 Mar 2022 16:22:12 +0000
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On Thu, Mar 10, 2022 at 01:52:24PM -0600, nick.hawkins@hpe.com wrote:
>> From: Nick Hawkins <nick.hawkins@hpe.com>>
>>=20
>> Creating binding for gxp timer in device tree hpe,gxp-timer Although=20
>> there are multiple times on the SoC we are only enabling one at this=20
>> time.
>>=20
>> Signed-off-by: Nick Hawkins <nick.hawkins@hpe.com>>
>>=20
>> ----
>>=20
>> v2:
>>  *Removed maintainer change from patch  *Verified there was no=20
>> compilation errors  *Added reference code in separate patch of=20
>> patchset
>> ---
>>  .../bindings/timer/hpe,gxp-timer.yaml         | 45 +++++++++++++++++++
>>  1 file changed, 45 insertions(+)
>>  create mode 100644=20
>> Documentation/devicetree/bindings/timer/hpe,gxp-timer.yaml
>>=20
>> diff --git=20
>> a/Documentation/devicetree/bindings/timer/hpe,gxp-timer.yaml=20
>> b/Documentation/devicetree/bindings/timer/hpe,gxp-timer.yaml
>> new file mode 100644
>> index 000000000000..1f4e345c5fb8
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/timer/hpe,gxp-timer.yaml
>> @@ -0,0 +1,45 @@
>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2
>> +---
>> +$id:=20
>> +INVALID URI REMOVED
>> +xp-timer.yaml*__;Iw!!NpxR!yaItMPvjqEf3fKyp1xDQAzawRQDd8uDGTNKMlVPpn5Y
>> +56IUABMYbali7jonBl20K$
>> +$schema:=20
>> +INVALID URI REMOVED
>> +aml*__;Iw!!NpxR!yaItMPvjqEf3fKyp1xDQAzawRQDd8uDGTNKMlVPpn5Y56IUABMYba
>> +li7jmX565-G$
>> +
>> +title: HPE GXP TIMER
>> +
>> +maintainers:
>> +  - Nick Hawkins <nick.hawkins@hpe.com>>
>> +  - Jean-Marie Verdun <verdun@hpe.com>>
>> +
>> +properties:
>> +  compatible:
>> +    const: hpe,gxp-timer
>> +
>> +  reg:
>> +    items:
>> +      - description: T0CNT register
>> +      - description: T0CS register
>> +      - description: TIMELO register

> Is the spec public to know what T0CNT, T0CS, and TIMELO are?
No it is not, should I not mention the register descriptions at all?

>> +
>> +  interrupts:
>> +    maxItems: 1
>> +
>> +  clock-frequency:
>> +    description: The frequency of the clock that drives the counter, in=
 Hz.
>> +
>> +required:
>> +  - compatible
>> +  - reg
>> +  - interrupts
>> +  - clock-frequency
>> +
>> +additionalProperties: false
>> +
>> +examples:
>> +  - |
>> +    timer@10003000 {
>> +        compatible =3D "hpe,gxp-timer";
>> +        reg =3D <0xc0000080 0x1>>, <0xc0000094 0x01>>, <0xc0000088 0x08=
>>;

> Based on the driver these are 4 bytes, 1 byte, 4 bytes in size.

> Are there other registers in 0x80-0x95 range or do these offsets change i=
n other chips? If not, just 1 entry covering the whole thing would be bette=
r.
There are other registers in this range that cover different timers/clocks,=
 for the most part between chip generations the offsets remain the same unl=
ess there is an architectural issue.
Can you provide a quick example of what one entry would be?

>> +        interrupts =3D <0>>;
>> +        interrupt-parent =3D <&vic0>>;
>> +        clock-frequency =3D <400000000>>;
>> +    };
>> --
>> 2.17.1
>>=20
>>=20

Regards,

Nick Hawkins=20