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(unknown [213.135.10.150]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-384) server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by ssl.serverraum.org (Postfix) with ESMTPSA id 51309223EA; Sun, 13 Mar 2022 01:25:41 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=walle.cc; s=mail2016061301; t=1647131141; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=Om+Fp1RFdxau+QHT4ZTv6VQABvlFxAGNLV7Mt6x5j5M=; b=MOkjsAoJ4vbz9eNZJwCs8DiwkX4djmNe7/f4Nv3tmKd78E6lyBK/Cjajb5sPnw4HePNpwE uHHrumTc1ExBkAbfzP2t0p7LPcyz4d4w0O8fY1o9wUT0H9okSvwHWCHgh0d4LKTnXx/taf gB6xu1l1s+reuLMy9lmEq9sDvmcySE0= From: Michael Walle To: "David S . Miller" , Jakub Kicinski , Rob Herring , Krzysztof Kozlowski , Andrew Lunn , Heiner Kallweit , Russell King Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Michael Walle Subject: [PATCH net-next v2 1/3] dt-bindings: net: mscc-miim: add lan966x compatible Date: Sun, 13 Mar 2022 01:25:34 +0100 Message-Id: <20220313002536.13068-2-michael@walle.cc> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220313002536.13068-1-michael@walle.cc> References: <20220313002536.13068-1-michael@walle.cc> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The MDIO controller has support to release the internal PHYs from reset by specifying a second memory resource. This is different between the currently supported SparX-5 and the LAN966x. Add a new compatible to distiguish between these two. Signed-off-by: Michael Walle --- Documentation/devicetree/bindings/net/mscc-miim.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/net/mscc-miim.txt b/Documentation/devicetree/bindings/net/mscc-miim.txt index 7104679cf59d..a9efff252ca6 100644 --- a/Documentation/devicetree/bindings/net/mscc-miim.txt +++ b/Documentation/devicetree/bindings/net/mscc-miim.txt @@ -2,7 +2,7 @@ Microsemi MII Management Controller (MIIM) / MDIO ================================================= Properties: -- compatible: must be "mscc,ocelot-miim" +- compatible: must be "mscc,ocelot-miim" or "mscc,lan966x-miim" - reg: The base address of the MDIO bus controller register bank. Optionally, a second register bank can be defined if there is an associated reset register for internal PHYs -- 2.30.2