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Subject: Re: [PATCH] drm/bridge: synopsys/dw-hdmi: set cec clock rate
From:   Piotr Oniszczuk <piotr.oniszczuk@gmail.com>
In-Reply-To: <20220126202427.3047814-1-pgwipeout@gmail.com>
Date:   Sun, 13 Mar 2022 11:12:59 +0100
Cc:     Andrzej Hajda <andrzej.hajda@intel.com>,
        Neil Armstrong <narmstrong@baylibre.com>,
        Robert Foss <robert.foss@linaro.org>,
        Laurent Pinchart <Laurent.pinchart@ideasonboard.com>,
        Jonas Karlman <jonas@kwiboo.se>,
        Jernej Skrabec <jernej.skrabec@gmail.com>,
        David Airlie <airlied@linux.ie>,
        Daniel Vetter <daniel@ffwll.ch>,
        Pierre-Hugues Husson <phh@phh.me>,
        Archit Taneja <architt@codeaurora.org>,
        Sascha Hauer <s.hauer@pengutronix.de>,
        Robin Murphy <robin.murphy@arm.com>,
        "open list:ARM/Rockchip SoC..." <linux-rockchip@lists.infradead.org>,
        =?utf-8?Q?Heiko_St=C3=BCbner?= <heiko@sntech.de>,
        dri-devel@lists.freedesktop.org,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
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Message-Id: <3AFD1DD4-AF0A-4ECC-B4F5-E6BD6B9F1BB7@gmail.com>
References: <20220126202427.3047814-1-pgwipeout@gmail.com>
To:     Peter Geis <pgwipeout@gmail.com>
Precedence: bulk


> Wiadomo=C5=9B=C4=87 napisana przez Peter Geis <pgwipeout@gmail.com> w =
dniu 26.01.2022, o godz. 21:24:
>=20
> The hdmi-cec clock must be 32khz in order for cec to work correctly.
> Ensure after enabling the clock we set it in order for the hardware to
> work as expected.
> Warn on failure, in case this is a static clock that is slighty off.
> Fixes hdmi-cec support on Rockchip devices.
>=20
> Fixes: ebe32c3e282a ("drm/bridge: synopsys/dw-hdmi: Enable cec clock")
>=20
> Signed-off-by: Peter Geis <pgwipeout@gmail.com>
> ---
> drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 7 +++++++
> 1 file changed, 7 insertions(+)
>=20
> diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c =
b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
> index 54d8fdad395f..1a96da60e357 100644
> --- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
> +++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
> @@ -48,6 +48,9 @@
>=20
> #define HDMI14_MAX_TMDSCLK	340000000
>=20
> +/* HDMI CEC needs a clock rate of 32khz */
> +#define HDMI_CEC_CLK_RATE	32768
> +
> enum hdmi_datamap {
> 	RGB444_8B =3D 0x01,
> 	RGB444_10B =3D 0x03,
> @@ -3347,6 +3350,10 @@ struct dw_hdmi *dw_hdmi_probe(struct =
platform_device *pdev,
> 				ret);
> 			goto err_iahb;
> 		}
> +
> +		ret =3D clk_set_rate(hdmi->cec_clk, HDMI_CEC_CLK_RATE);
> +		if (ret)
> +			dev_warn(hdmi->dev, "Cannot set HDMI cec clock =
rate: %d\n", ret);
> 	}
>=20
> 	/* Product and revision IDs */
> --=20
> 2.25.1
>=20
>=20
> _______________________________________________
> Linux-rockchip mailing list
> Linux-rockchip@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-rockchip

Peter,

On my 5.17-rc7 with applied rk356x VOP2 v8 series - this patch makes CEC =
working on rk3566.
Unfortunately it breaks working ok CEC on rk3399 rockpi-4b.

Reverting this patch brings back CEC on rk3399 - but rk3366 becomes with =
non working CEC
=20
I'm not sure how to move forward with this....
=20
br=