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References: <20220126202427.3047814-1-pgwipeout@gmail.com> <3AFD1DD4-AF0A-4ECC-B4F5-E6BD6B9F1BB7@gmail.com>
In-Reply-To: <3AFD1DD4-AF0A-4ECC-B4F5-E6BD6B9F1BB7@gmail.com>
From:   Peter Geis <pgwipeout@gmail.com>
Date:   Sun, 13 Mar 2022 08:56:55 -0400
Message-ID: <CAMdYzYq06QSmFAwCuTmBYy4LfQAQDxzx2PGc8HOB1iEjxXHGyg@mail.gmail.com>
Subject: Re: [PATCH] drm/bridge: synopsys/dw-hdmi: set cec clock rate
To:     Piotr Oniszczuk <piotr.oniszczuk@gmail.com>
Cc:     Andrzej Hajda <andrzej.hajda@intel.com>,
        Neil Armstrong <narmstrong@baylibre.com>,
        Robert Foss <robert.foss@linaro.org>,
        Laurent Pinchart <Laurent.pinchart@ideasonboard.com>,
        Jonas Karlman <jonas@kwiboo.se>,
        Jernej Skrabec <jernej.skrabec@gmail.com>,
        David Airlie <airlied@linux.ie>,
        Daniel Vetter <daniel@ffwll.ch>,
        Pierre-Hugues Husson <phh@phh.me>,
        Archit Taneja <architt@codeaurora.org>,
        Sascha Hauer <s.hauer@pengutronix.de>,
        Robin Murphy <robin.murphy@arm.com>,
        "open list:ARM/Rockchip SoC..." <linux-rockchip@lists.infradead.org>,
        =?UTF-8?Q?Heiko_St=C3=BCbner?= <heiko@sntech.de>,
        dri-devel@lists.freedesktop.org,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
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On Sun, Mar 13, 2022 at 6:13 AM Piotr Oniszczuk
<piotr.oniszczuk@gmail.com> wrote:
>
>
>
> > Wiadomo=C5=9B=C4=87 napisana przez Peter Geis <pgwipeout@gmail.com> w d=
niu 26.01.2022, o godz. 21:24:
> >
> > The hdmi-cec clock must be 32khz in order for cec to work correctly.
> > Ensure after enabling the clock we set it in order for the hardware to
> > work as expected.
> > Warn on failure, in case this is a static clock that is slighty off.
> > Fixes hdmi-cec support on Rockchip devices.
> >
> > Fixes: ebe32c3e282a ("drm/bridge: synopsys/dw-hdmi: Enable cec clock")
> >
> > Signed-off-by: Peter Geis <pgwipeout@gmail.com>
> > ---
> > drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 7 +++++++
> > 1 file changed, 7 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/dr=
m/bridge/synopsys/dw-hdmi.c
> > index 54d8fdad395f..1a96da60e357 100644
> > --- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
> > +++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
> > @@ -48,6 +48,9 @@
> >
> > #define HDMI14_MAX_TMDSCLK    340000000
> >
> > +/* HDMI CEC needs a clock rate of 32khz */
> > +#define HDMI_CEC_CLK_RATE    32768
> > +
> > enum hdmi_datamap {
> >       RGB444_8B =3D 0x01,
> >       RGB444_10B =3D 0x03,
> > @@ -3347,6 +3350,10 @@ struct dw_hdmi *dw_hdmi_probe(struct platform_de=
vice *pdev,
> >                               ret);
> >                       goto err_iahb;
> >               }
> > +
> > +             ret =3D clk_set_rate(hdmi->cec_clk, HDMI_CEC_CLK_RATE);
> > +             if (ret)
> > +                     dev_warn(hdmi->dev, "Cannot set HDMI cec clock ra=
te: %d\n", ret);
> >       }
> >
> >       /* Product and revision IDs */
> > --
> > 2.25.1
> >
> >
> > _______________________________________________
> > Linux-rockchip mailing list
> > Linux-rockchip@lists.infradead.org
> > http://lists.infradead.org/mailman/listinfo/linux-rockchip
>
> Peter,
>
> On my 5.17-rc7 with applied rk356x VOP2 v8 series - this patch makes CEC =
working on rk3566.
> Unfortunately it breaks working ok CEC on rk3399 rockpi-4b.
>
> Reverting this patch brings back CEC on rk3399 - but rk3366 becomes with =
non working CEC
>
> I'm not sure how to move forward with this....

I was worried about that, thanks for testing it.
Can you send me the cec_clk rate before and after this patch?

>
> br