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Date:   Mon, 14 Mar 2022 15:11:40 +0200
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Subject: Re: [PATCH] mmc: core: Set HS clock speed before sending HS CMD13
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To:     Brian Norris <briannorris@chromium.org>,
        Ulf Hansson <ulf.hansson@linaro.org>
Cc:     linux-kernel@vger.kernel.org,
        Douglas Anderson <dianders@chromium.org>,
        Shawn Lin <shawn.lin@rock-chips.com>, linux-mmc@vger.kernel.org
References: <20220310125636.1.I484f4ee35609f78b932bd50feed639c29e64997e@changeid>
From:   Adrian Hunter <adrian.hunter@intel.com>
Organization: Intel Finland Oy, Registered Address: PL 281, 00181 Helsinki,
 Business Identity Code: 0357606 - 4, Domiciled in Helsinki
In-Reply-To: <20220310125636.1.I484f4ee35609f78b932bd50feed639c29e64997e@changeid>
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On 10.3.2022 22.56, Brian Norris wrote:
> Way back in commit 4f25580fb84d ("mmc: core: changes frequency to
> hs_max_dtr when selecting hs400es"), Rockchip engineers noticed that
> some eMMC don't respond to SEND_STATUS commands very reliably if they're
> still running at a low initial frequency. As mentioned in that commit,
> JESD84-B51 P49 suggests a sequence in which the host:
> 1. sets HS_TIMING
> 2. bumps the clock ("<= 52 MHz")
> 3. sends further commands
> 
> It doesn't exactly require that we don't use a lower-than-52MHz
> frequency, but in practice, these eMMC don't like it.
> 
> Anyway, the aforementioned commit got that right for HS400ES, but the
> refactoring in 53e60650f74e ("mmc: core: Allow CMD13 polling when
> switching to HS mode for mmc") messed that back up again, by reordering
> step 2 after step 3.

That description might not be accurate.

It looks like 4f25580fb84d did not have the intended effect because
CMD13 was already being sent by mmc_select_hs(), still before increasing
the frequency.  53e60650f74e just kept that behaviour.

> 
> Let's fix that, and also apply the same logic to HS200/400, where this
> eMMC has problems too.
> 
> This resolves errors like this seen when booting some RK3399 Gru/Scarlet
> systems:
> 
> [    2.058881] mmc1: CQHCI version 5.10
> [    2.097545] mmc1: SDHCI controller on fe330000.mmc [fe330000.mmc] using ADMA
> [    2.209804] mmc1: mmc_select_hs400es failed, error -84
> [    2.215597] mmc1: error -84 whilst initialising MMC card
> [    2.417514] mmc1: mmc_select_hs400es failed, error -110
> [    2.423373] mmc1: error -110 whilst initialising MMC card
> [    2.605052] mmc1: mmc_select_hs400es failed, error -110
> [    2.617944] mmc1: error -110 whilst initialising MMC card
> [    2.835884] mmc1: mmc_select_hs400es failed, error -110
> [    2.841751] mmc1: error -110 whilst initialising MMC card
> 
> Fixes: 53e60650f74e ("mmc: core: Allow CMD13 polling when switching to HS mode for mmc")
> Cc: Shawn Lin <shawn.lin@rock-chips.com>
> Signed-off-by: Brian Norris <briannorris@chromium.org>
> ---
> 
>  drivers/mmc/core/mmc.c | 15 +++++++++++++--
>  1 file changed, 13 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/mmc/core/mmc.c b/drivers/mmc/core/mmc.c
> index 13abfcd130a5..821b90caba2f 100644
> --- a/drivers/mmc/core/mmc.c
> +++ b/drivers/mmc/core/mmc.c
> @@ -1390,12 +1390,17 @@ static int mmc_select_hs400es(struct mmc_card *card)
>  	}
>  
>  	mmc_set_timing(host, MMC_TIMING_MMC_HS);
> +
> +	/*
> +	 * Bump to HS frequency. Some cards don't handle SEND_STATUS reliably
> +	 * at the initial frequency.
> +	 */
> +	mmc_set_clock(host, card->ext_csd.hs_max_dtr);
> +
>  	err = mmc_switch_status(card, true);
>  	if (err)
>  		goto out_err;
>  
> -	mmc_set_clock(host, card->ext_csd.hs_max_dtr);
> -
>  	/* Switch card to DDR with strobe bit */
>  	val = EXT_CSD_DDR_BUS_WIDTH_8 | EXT_CSD_BUS_WIDTH_STROBE;
>  	err = mmc_switch(card, EXT_CSD_CMD_SET_NORMAL,
> @@ -1487,6 +1492,12 @@ static int mmc_select_hs200(struct mmc_card *card)
>  		old_timing = host->ios.timing;
>  		mmc_set_timing(host, MMC_TIMING_MMC_HS200);
>  
> +		/*
> +		 * Bump to HS frequency. Some cards don't handle SEND_STATUS
> +		 * reliably at the initial frequency.
> +		 */
> +		mmc_set_clock(host, card->ext_csd.hs_max_dtr);

Is card->ext_csd.hs_max_dtr better than card->ext_csd.hs200_max_dtr here?

> +
>  		/*
>  		 * For HS200, CRC errors are not a reliable way to know the
>  		 * switch failed. If there really is a problem, we would expect