Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:18 as permitted sender) client-ip=2620:137:e000::1:18;
Date:   Wed, 16 Mar 2022 11:07:48 -0300
From:   Jason Gunthorpe <jgg@nvidia.com>
To:     "Tian, Kevin" <kevin.tian@intel.com>
Cc:     Robin Murphy <robin.murphy@arm.com>,
        Jacob Pan <jacob.jun.pan@linux.intel.com>,
        "iommu@lists.linux-foundation.org" <iommu@lists.linux-foundation.org>,
        LKML <linux-kernel@vger.kernel.org>,
        Joerg Roedel <joro@8bytes.org>,
        Christoph Hellwig <hch@infradead.org>,
        Lu Baolu <baolu.lu@linux.intel.com>,
        Jean-Philippe Brucker <jean-philippe@linaro.com>,
        "Luck, Tony" <tony.luck@intel.com>,
        "Jiang, Dave" <dave.jiang@intel.com>,
        "Raj, Ashok" <ashok.raj@intel.com>,
        "Zanussi, Tom" <tom.zanussi@intel.com>,
        "Kumar, Sanjay K" <sanjay.k.kumar@intel.com>,
        "Pan, Jacob jun" <jacob.jun.pan@intel.com>,
        "Williams, Dan J" <dan.j.williams@intel.com>
Subject: Re: [PATCH v2 5/8] iommu: Add PASID support for DMA mapping API users
Message-ID: <20220316140748.GF11336@nvidia.com>
References: <20220315050713.2000518-1-jacob.jun.pan@linux.intel.com>
 <20220315050713.2000518-6-jacob.jun.pan@linux.intel.com>
 <00286dbb-fe73-3604-4dec-340eb91912c3@arm.com>
 <20220315142216.GV11336@nvidia.com>
 <BN9PR11MB527697CA21B1D28BBD0BE0DC8C119@BN9PR11MB5276.namprd11.prod.outlook.com>
Content-Type: text/plain; charset=us-ascii
Content-Disposition: inline
In-Reply-To: <BN9PR11MB527697CA21B1D28BBD0BE0DC8C119@BN9PR11MB5276.namprd11.prod.outlook.com>
MIME-Version: 1.0
X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1
X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?AL6ZPSGl3wf+JOngQq/BAUzI1rdF7eUnGXC4Hb6VRE5Da0Hy0iijpYpUL8X7?=
 =?us-ascii?Q?P1evcG27AQ9WLiLfGtFOzJWMpKZum8xHIVniPONawBfqHqih6pvB98WK3EKu?=
 =?us-ascii?Q?ehfdbsrAeDh4wGXdTpA+xevgLoR+nR9EwstaPCGhbXexbyPL/r7X/odmdckA?=
 =?us-ascii?Q?+UNInSlCMv9bI59iC4+ZImv7Mie3XPfBWGgQKE9bxoggt+EiuVUUfR5VCB5b?=
 =?us-ascii?Q?bF/MrFF+j/uWr+brDXjdWz3Vcku00ATG0+a5ylG2KAPyLU5lea0KPMc59LdC?=
 =?us-ascii?Q?ra96207p81PGQhilpzOfQekLefY2WU2W/rT8Uv6+P5fSbY4H00bVVyfOPoGe?=
 =?us-ascii?Q?pWN+FFhJaNvbH31WtoiaVoMowfJ/4+e2N12VOddk4z93nK4pQ/JQWxxJOLZ1?=
 =?us-ascii?Q?WEdWP6qXfbd4QT++DdQrq05M2vOT5eCYKugkqNBPLS7ks4MCvPLOFCF3e1+k?=
 =?us-ascii?Q?tHcf8VUs+N83klJ8WcJHuoyV/EPIMFX0Pi2N66i6199JnCokXAosRbclekRw?=
 =?us-ascii?Q?X8MmQK/pbTNhXqI2Rst7AB8T3eRnmk3azM00UNN//lymCMMedCIWHGVtuFzr?=
 =?us-ascii?Q?QpHLHcZijAgDPoZJnNp6mlduTgMbbpvWD+7WnVCVDNIwfpaVQihydTQmERz3?=
 =?us-ascii?Q?artvtnPwsnvCywEzcwsee5fT3nKah9hT5EA5rsdKwnKVxO2eqMne8RU228u/?=
 =?us-ascii?Q?+9cH02YxCANpHrQhW05xOs/mAOYdZGS+qt0YFMS/Yl2LNWT4NWQyJlkYCcEZ?=
 =?us-ascii?Q?nQfeVQNnqUfDoKX7HbmaehC3w6yoW92/tgzE28BC0uBekFpKBStzKFhnhmQ7?=
 =?us-ascii?Q?JCqDgqZ9LjfralrBOdnS8xgDyHyrExGrb475UCB1O1Q5pdPsNGS1oX/Z03gc?=
 =?us-ascii?Q?OGKVc86TOxaervYxqyni0Lphn7H1AcXAaigaTpB7ObGbSfDWB8BbAbX/Y+9M?=
 =?us-ascii?Q?2m12+2OQ8IECWIYzsMRDgGOqtt5c7vjKcGDql0Xxf0CpvbbZzDPfvzYI/axi?=
 =?us-ascii?Q?ihl0QHulSLp8NdK4Vbn/a3NVyFO5N8b0Sn+pL+9yeYtEXw5FAglocK1Y4FQJ?=
 =?us-ascii?Q?IQskIVo3RZC0eFOKMiULwAJ2uAyK9dbbxMCTan+JiKnCCiuPcvcDD5Ne4p5I?=
 =?us-ascii?Q?Bp/r6V0snFq/Seb/2GS5RSyiXNdmUsttXvj0WIudSXobGCflOoujik+IymAk?=
 =?us-ascii?Q?f/7vlL1ptkwawwg29lkm1I8IknFnIXfh5bT5KdYOVjbKV/9OkU4FjJyDEGZ7?=
 =?us-ascii?Q?qaP82IktVqg3VmnZpPb986gLQ43BWT5rMgZj5yngbdQApfMfC3GhSw8VpeeB?=
 =?us-ascii?Q?HtLeztDqPa3dUDJdbaHWKKQOIYDn1SUDgpXFD6cuKbyvesrIHBywFsEldycY?=
 =?us-ascii?Q?9XgdaEb0YV2heGu+uIFvdJxSVT5zmVi8SVndWiWCR4FHDnCmlLlM9mxNw+vL?=
 =?us-ascii?Q?eyJUXM89d7RQSpakijQ6yhcNp1B3hjQK?=
X-OriginatorOrg: Nvidia.com
X-MS-Exchange-CrossTenant-Network-Message-Id: ddbfc6a7-8b56-47b4-20eb-08da07565afd
X-MS-Exchange-CrossTenant-AuthSource: MN2PR12MB4192.namprd12.prod.outlook.com
X-MS-Exchange-CrossTenant-AuthAs: Internal
X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Mar 2022 14:07:50.3497
 (UTC)
X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted
X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a
X-MS-Exchange-CrossTenant-MailboxType: HOSTED
X-MS-Exchange-CrossTenant-UserPrincipalName: aTbLXn6KAmSGypI2RIwASd4KvMmEG3bnm/BynUceQP+ijFZq9Qhpwlw5wqQE4c6H
X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH2PR12MB5545
X-Spam-Status: No, score=-3.5 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH,
	DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,
	MAILING_LIST_MULTI,RDNS_NONE,SPF_HELO_NONE,T_SCC_BODY_TEXT_LINE
	autolearn=unavailable autolearn_force=no version=3.4.6
X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on
	lindbergh.monkeyblade.net
Precedence: bulk
List-ID: <linux-kernel.vger.kernel.org>
X-Mailing-List: linux-kernel@vger.kernel.org

On Wed, Mar 16, 2022 at 08:41:27AM +0000, Tian, Kevin wrote:

> 1) When the kernel wants a more scalable way of using IDXD e.g. having
> multiple CPUs simultaneously submitting works in a lockless way to a 
> shared work queue via a new instruction (ENQCMD) which carries
> PASID.

IMHO the misdesign is the CPU can't submit work with ENQCMD from
kernel space that will do DMA on the RID.

> 2) When the host wants to share a workqueue between multiple VMs.
> In that case the virtual IDXD device exposed to each VM will only support
> the shared workqueue mode. Only in this case the DMA API in the
> guest must be attached by a PASID as ENQCMD is the only way to submit
> works.

It is the same issue - if ENQCMD had 'excute on the RID' then the
virtualization layer could translate that to 'execute on this PASID
setup by the hypervisor' and the kernel would not see additional
differences between SIOV and physical devices. IMHO mandatory kernel
PASID support in the guest just to support the kernel doing DMA to a
device is not nice.

Jason