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[2620:137:e000::1:18]) by mx.google.com with ESMTPS id k21-20020a056a00169500b004f7d7ba9136si3886141pfc.195.2022.03.16.20.36.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 16 Mar 2022 20:36:43 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:18 as permitted sender) client-ip=2620:137:e000::1:18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id BE85754BCC; Wed, 16 Mar 2022 20:32:10 -0700 (PDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1351239AbiCPSXo (ORCPT + 99 others); Wed, 16 Mar 2022 14:23:44 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48562 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237492AbiCPSXn (ORCPT ); Wed, 16 Mar 2022 14:23:43 -0400 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id AAF045468F; Wed, 16 Mar 2022 11:22:28 -0700 (PDT) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 59AF81476; Wed, 16 Mar 2022 11:22:28 -0700 (PDT) Received: from [10.57.42.204] (unknown [10.57.42.204]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 6A6813F766; Wed, 16 Mar 2022 11:22:26 -0700 (PDT) Message-ID: <5ef1c30a-1740-00cc-ad16-4b1c1b02fca4@arm.com> Date: Wed, 16 Mar 2022 18:22:21 +0000 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; rv:91.0) Gecko/20100101 Thunderbird/91.6.2 Subject: Re: [PATCH] thunderbolt: Stop using iommu_present() Content-Language: en-GB To: "Limonciello, Mario" , Mika Westerberg Cc: "michael.jamet@intel.com" , "linux-usb@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "YehezkelShB@gmail.com" , "iommu@lists.linux-foundation.org" , "andreas.noever@gmail.com" , "hch@lst.de" References: <16852eb2-98bb-6337-741f-8c2f06418b08@arm.com> <3bb6a2f8-005b-587a-7d7a-7a9a5391ec05@arm.com> From: Robin Murphy In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,NICE_REPLY_A, RDNS_NONE,SPF_HELO_NONE,T_SCC_BODY_TEXT_LINE autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 2022-03-16 17:53, Limonciello, Mario wrote: > [Public] > >>>>> >>>>> There is a way to figure out the "tunneled" PCIe ports by looking at >>>>> certain properties and we do that already actually. The BIOS has the >>>>> following under these ports: >>>>> >>>>> >> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fdocs >>>>> .microsoft.com%2Fen-us%2Fwindows- >> hardware%2Fdrivers%2Fpci%2Fdsd- >>>>> for-pcie-root-ports%23identifying-externally-exposed-pcie-root- >>>>> >> ports&data=04%7C01%7Cmario.limonciello%40amd.com%7C0465d319a >>>>> >> 6684335d9c208da07710e7c%7C3dd8961fe4884e608e11a82d994e183d%7C0%7 >>>>> >> C0%7C637830479402895833%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4w >>>>> >> LjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000&am >>>>> >> p;sdata=z6hpYGpj%2B%2BVvz9d6MXiO4N66PUm4zwhOdI%2Br6l3PjhQ%3D >>>>> &reserved=0 >>>>> >>>>> and the ports will have dev->external_facing set to 1. Perhaps looking >>>>> at that field helps here? >>>> >>>> External facing isn't a guarantee from the firmware though. It's >> something we >>>> all expect in practice, but I think it's better to look at the ones that are >> from >>>> the _DSD usb4-host-interface to be safer. >>> >>> Right but then we have the discrete ones with the DVSEC that exposes the >>> tunneled ports :( >>> > > Can the USB4 CM make the device links in the DVSEC case perhaps too? I would > think we want that anyway to control device suspend ordering. > > If I had something discrete to try I'd dust off the DVSEC patch I wrote before to > try it, but alas all I have is integrated stuff on my hand. > >>>> Mika, you might not have seen it yet, but I sent a follow up diff in this >> thread >>>> to Robin's patch. If that looks good Robin can submit a v2 (or I'm happy to >> do >>>> so as well as I confirmed it helps my original intent too). >>> >>> I saw it now and I'm thinking are we making this unnecessary complex? I >>> mean Microsoft solely depends on the DMAR platform opt-in flag: >>> >>> >> > > I think Microsoft doesn't allow you to turn off the IOMMU though or put it in > passthrough through on the kernel command line. > >>> We also do turn on full IOMMU mappings in that case for devices that are >>> marked as external facing by the same firmware that provided the DMAR >>> bit. If the user decides to disable IOMMU from command line for instance >>> then we expect she knows what she is doing. >> >> Yeah, if external_facing is set correctly then we can safely expect the >> the IOMMU layer to do the right thing, so in that case it probably is OK >> to infer that if an IOMMU is present for the NHI then it'll be managing >> that whole bus hierarchy. What I'm really thinking about here is whether >> we can defend against a case when external_facing *isn't* set, so we >> treat the tunnelled ports as normal PCI buses, assume it's OK since >> we've got an IOMMU and everything else is getting translation domains by >> default, but then a Thunderbolt device shows up masquerading the VID:DID >> of something that gets a passthrough quirk, and thus tricks its way >> through the perceived protection. >> >> Robin. > > Unless it happened after 5.17-rc8 looking at the code I think that's Intel > specific behavior though at the moment (has_external_pci). I don't see it > in a generic layer. Ah, it's not necessarily the most obvious thing - pci_dev->external_facing gets propagated through to pci_dev->untrusted by set_pcie_untrusted(), and it's that that's then checked by iommu_get_def_domain_type() to enforce a translation domain regardless of default passthrough or quirks. It's then further checked by iommu-dma's dev_is_untrusted() to enforce bounce-buffering to avoid data leakage in sub-page mappings too. > In addition to the point Robin said about firmware not setting external facing > if the IOMMU was disabled on command line then iommu_dma_protection > would be showing the wrong values meaning userspace may choose to > authorize the device automatically in a potentially unsafe scenario. > > Even if the user "knew what they were doing", I would expect that we still > do our best to protect them from themselves and not advertise something > that will cause automatic authorization. Might it be reasonable for the Thunderbolt core to check early on if any tunnelled ports are not marked as external facing, and if so just tell the user that iommu_dma_protection is off the table and anything they authorise is at their own risk? Robin.