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Tue, 15 Mar 2022 09:18:54 -0700 (PDT) Date: Tue, 15 Mar 2022 11:18:53 -0500 From: Bjorn Andersson To: Bhupesh Sharma Cc: linux-arm-msm@vger.kernel.org, bhupesh.linux@gmail.com, agross@kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, maz@kernel.org, quic_mkshah@quicinc.com, linux-gpio@vger.kernel.org, linus.walleij@linaro.org, robh+dt@kernel.org, Vinod Koul , Rob Herring Subject: Re: [PATCH v2 3/4] arm64: dts: qcom: sm8150: Add pdc interrupt controller node Message-ID: References: <20220226184028.111566-1-bhupesh.sharma@linaro.org> <20220226184028.111566-4-bhupesh.sharma@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20220226184028.111566-4-bhupesh.sharma@linaro.org> X-Spam-Status: No, score=-2.0 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,RDNS_NONE,SPF_HELO_NONE,T_SCC_BODY_TEXT_LINE autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Sat 26 Feb 12:40 CST 2022, Bhupesh Sharma wrote: > Add pdc interrupt controller for sm8150. > > Cc: Maulik Shah > Cc: Bjorn Andersson > Cc: Vinod Koul > Cc: Rob Herring > Signed-off-by: Bhupesh Sharma > --- > arch/arm64/boot/dts/qcom/sm8150.dtsi | 10 ++++++++++ > 1 file changed, 10 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi > index 6012322a5984..aaeacd379460 100644 > --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi > +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi > @@ -1626,6 +1626,16 @@ system-cache-controller@9200000 { > interrupts = ; > }; > > + pdc: interrupt-controller@b220000 { > + compatible = "qcom,sm8150-pdc", "qcom,pdc"; > + reg = <0 0x0b220000 0 0x400>; > + qcom,pdc-ranges = <0 480 94>, <94 609 31>, > + <125 63 1>; When I look at the platform documentation I get the impression that this should be: <0 480 94>, <94 609 32>; Can you confirm that the last signal is correctly described? Regards, Bjorn > + #interrupt-cells = <2>; > + interrupt-parent = <&intc>; > + interrupt-controller; > + }; > + > ufs_mem_hc: ufshc@1d84000 { > compatible = "qcom,sm8150-ufshc", "qcom,ufshc", > "jedec,ufs-2.0"; > -- > 2.35.1 >