Received: by 2002:a05:6a10:413:0:0:0:0 with SMTP id 19csp936564pxp; Wed, 16 Mar 2022 21:55:17 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwzpBFEjGDYmc19NW354kQdKN2hY0EuBqO1N+TwrB4Res/9Pbu8/ejhSK6LeZEVIXquOUrW X-Received: by 2002:a63:2b08:0:b0:37c:4e14:31bd with SMTP id r8-20020a632b08000000b0037c4e1431bdmr2290291pgr.6.1647492917580; Wed, 16 Mar 2022 21:55:17 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1647492917; cv=none; d=google.com; s=arc-20160816; b=LzBqSdAi4F61zZ3kEANaGamRRIrHMvby4wkYWFWFP+gJT/GSnQHNWeS+50MohPa3AW ArGv89R1k/zOcPq6Dw1Ou/y5t5BeU7oXVG09wxXT6V/hbsimrozHFV5lfIe8JsMJYC4M ze+LmNGX/vWYi+JbWM8vnvmTUCYCZGQHz85h/OgxTAbx5OLGK4oq+XiHJzbqfkT5cMw/ nNkPMPhjG1SXtezj+cVJppHU8uhsTZQckIt3Mv39lP87UAUiyCuhVk+YOC7fVZrz2DC3 5nGmOaSHs24S0twh866nBtffRCNlJrcnScLcwLjfpI9G6EhY78lnMDpfeqjE9nI6T7up tzaw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:in-reply-to :organization:from:references:cc:to:content-language:subject :user-agent:mime-version:date:message-id:dkim-signature; bh=ytX2SFvM53HE0N3pYke/nVlK3T7iEr7di47zL9BakSQ=; b=T/E/wpCjD9PWImtPurqjUJcgZHy2lXpEZrdEKzn2cNRvJfKlBx5u3LsTLIw/kP1kUX etHtZRaW6Ezvqv38Cr27k9UyBtDOsy5vTypVVidGGT+Cb/XwJyJfUsQc2chXTd+GhJ0V ijd4AjC/MDKKXXgRjsJGaaUOwnanalwJe/KBwabyYEcv04EZ9oNRu2Pc55TzJMaQnTE+ R2kR3sAbIU8lUzRJwLEBytJ7pZrCkexhQq5ZF8Fe0i2igWmxi6A+poRaVjV/65dOM2wX oRlJdPCZWQUsJgc2ive6b05MfVVlnypgOuWakQaDAjKyyg8YpyZHcBLFYm9C57wrIGFA quVQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcdkim header.b=ntSXzeCr; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Return-Path: Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id k31-20020a634b5f000000b003816043ef45si1053813pgl.314.2022.03.16.21.55.04; Wed, 16 Mar 2022 21:55:17 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcdkim header.b=ntSXzeCr; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1344827AbiCPPy1 (ORCPT + 99 others); Wed, 16 Mar 2022 11:54:27 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39484 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240847AbiCPPyW (ORCPT ); Wed, 16 Mar 2022 11:54:22 -0400 Received: from alexa-out-sd-01.qualcomm.com (alexa-out-sd-01.qualcomm.com [199.106.114.38]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6D35D17E0D; Wed, 16 Mar 2022 08:53:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1647445987; x=1678981987; h=message-id:date:mime-version:subject:to:cc:references: from:in-reply-to:content-transfer-encoding; bh=ytX2SFvM53HE0N3pYke/nVlK3T7iEr7di47zL9BakSQ=; b=ntSXzeCrFQlF+fNsrIQBnsllg3kABjFx14Wg3lqY9hom/5qFEefcQulu q8hvcipD68+0UsLrCAF0SG7TLIZoVoD/zx249jdQtRHQjqPYuRcIgUfbO K4uWtjpPBWJoSKlMlwbiE4a175BNx444QFAI7PbPkI0I/2Jcd9CC177Uy E=; Received: from unknown (HELO ironmsg05-sd.qualcomm.com) ([10.53.140.145]) by alexa-out-sd-01.qualcomm.com with ESMTP; 16 Mar 2022 08:53:06 -0700 X-QCInternal: smtphost Received: from nasanex01c.na.qualcomm.com ([10.47.97.222]) by ironmsg05-sd.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Mar 2022 08:53:06 -0700 Received: from nalasex01a.na.qualcomm.com (10.47.209.196) by nasanex01c.na.qualcomm.com (10.47.97.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Wed, 16 Mar 2022 08:53:05 -0700 Received: from [10.216.40.72] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Wed, 16 Mar 2022 08:52:59 -0700 Message-ID: <0b68bc4c-62e3-d40f-3114-0c6864c01f1a@quicinc.com> Date: Wed, 16 Mar 2022 21:22:56 +0530 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:91.0) Gecko/20100101 Thunderbird/91.6.1 Subject: Re: [PATCH v11 4/7] pinctrl: qcom: Update lpi pin group custiom functions with framework generic functions Content-Language: en-US To: Bjorn Andersson CC: , , , , , , , , , , , , , , , , Linus Walleij , , Venkata Prasad Potturu References: <1647359413-31662-1-git-send-email-quic_srivasam@quicinc.com> <1647359413-31662-5-git-send-email-quic_srivasam@quicinc.com> From: Srinivasa Rao Mandadapu Organization: Qualcomm In-Reply-To: Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 8bit X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,NICE_REPLY_A,RCVD_IN_DNSWL_MED, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 3/15/2022 10:15 PM, Bjorn Andersson wrote: Thanks for your time Bjorn!!! > On Tue 15 Mar 10:50 CDT 2022, Srinivasa Rao Mandadapu wrote: > >> Update custom pin group structure members with framework generic group_desc structure >> and replace the driver's custom pinctrl_ops with framework provided generic pin control >> group functions to avoid redundant code written in lpass lpi driver. >> >> Signed-off-by: Srinivasa Rao Mandadapu >> Co-developed-by: Venkata Prasad Potturu >> Signed-off-by: Venkata Prasad Potturu >> --- >> drivers/pinctrl/qcom/Kconfig | 1 + >> drivers/pinctrl/qcom/pinctrl-lpass-lpi.c | 98 +++++++++++++++----------------- >> 2 files changed, 48 insertions(+), 51 deletions(-) >> >> diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig >> index ca6f68a..31c4aa6 100644 >> --- a/drivers/pinctrl/qcom/Kconfig >> +++ b/drivers/pinctrl/qcom/Kconfig >> @@ -351,6 +351,7 @@ config PINCTRL_LPASS_LPI >> select PINMUX >> select PINCONF >> select GENERIC_PINCONF >> + select GENERIC_PINCTRL_GROUPS >> depends on GPIOLIB >> help >> This is the pinctrl, pinmux, pinconf and gpiolib driver for the >> diff --git a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c >> index 3c15f80..5e27a38 100644 >> --- a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c >> +++ b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c >> @@ -51,11 +51,11 @@ >> >> #define LPI_PINGROUP(id, soff, f1, f2, f3, f4) \ >> { \ >> - .name = "gpio" #id, \ >> - .pins = gpio##id##_pins, \ >> + .group.name = "gpio" #id, \ >> + .group.pins = gpio##id##_pins, \ >> .pin = id, \ >> .slew_offset = soff, \ >> - .npins = ARRAY_SIZE(gpio##id##_pins), \ >> + .group.num_pins = ARRAY_SIZE(gpio##id##_pins), \ >> .funcs = (int[]){ \ >> LPI_MUX_gpio, \ >> LPI_MUX_##f1, \ >> @@ -67,9 +67,7 @@ >> } >> >> struct lpi_pingroup { >> - const char *name; >> - const unsigned int *pins; >> - unsigned int npins; >> + struct group_desc group; >> unsigned int pin; >> /* Bit offset in slew register for SoundWire pins only */ >> int slew_offset; >> @@ -150,20 +148,20 @@ enum sm8250_lpi_functions { >> LPI_MUX__, >> }; >> >> -static const unsigned int gpio0_pins[] = { 0 }; >> -static const unsigned int gpio1_pins[] = { 1 }; >> -static const unsigned int gpio2_pins[] = { 2 }; >> -static const unsigned int gpio3_pins[] = { 3 }; >> -static const unsigned int gpio4_pins[] = { 4 }; >> -static const unsigned int gpio5_pins[] = { 5 }; >> -static const unsigned int gpio6_pins[] = { 6 }; >> -static const unsigned int gpio7_pins[] = { 7 }; >> -static const unsigned int gpio8_pins[] = { 8 }; >> -static const unsigned int gpio9_pins[] = { 9 }; >> -static const unsigned int gpio10_pins[] = { 10 }; >> -static const unsigned int gpio11_pins[] = { 11 }; >> -static const unsigned int gpio12_pins[] = { 12 }; >> -static const unsigned int gpio13_pins[] = { 13 }; >> +static int gpio0_pins[] = { 0 }; >> +static int gpio1_pins[] = { 1 }; >> +static int gpio2_pins[] = { 2 }; >> +static int gpio3_pins[] = { 3 }; >> +static int gpio4_pins[] = { 4 }; >> +static int gpio5_pins[] = { 5 }; >> +static int gpio6_pins[] = { 6 }; >> +static int gpio7_pins[] = { 7 }; >> +static int gpio8_pins[] = { 8 }; >> +static int gpio9_pins[] = { 9 }; >> +static int gpio10_pins[] = { 10 }; >> +static int gpio11_pins[] = { 11 }; >> +static int gpio12_pins[] = { 12 }; >> +static int gpio13_pins[] = { 13 }; >> static const char * const swr_tx_clk_groups[] = { "gpio0" }; >> static const char * const swr_tx_data_groups[] = { "gpio1", "gpio2", "gpio5" }; >> static const char * const swr_rx_clk_groups[] = { "gpio3" }; >> @@ -250,38 +248,10 @@ static int lpi_gpio_write(struct lpi_pinctrl *state, unsigned int pin, >> return 0; >> } >> >> -static int lpi_gpio_get_groups_count(struct pinctrl_dev *pctldev) >> -{ >> - struct lpi_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); >> - >> - return pctrl->data->ngroups; >> -} >> - >> -static const char *lpi_gpio_get_group_name(struct pinctrl_dev *pctldev, >> - unsigned int group) >> -{ >> - struct lpi_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); >> - >> - return pctrl->data->groups[group].name; >> -} >> - >> -static int lpi_gpio_get_group_pins(struct pinctrl_dev *pctldev, >> - unsigned int group, >> - const unsigned int **pins, >> - unsigned int *num_pins) >> -{ >> - struct lpi_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); >> - >> - *pins = pctrl->data->groups[group].pins; >> - *num_pins = pctrl->data->groups[group].npins; >> - >> - return 0; >> -} >> - >> static const struct pinctrl_ops lpi_gpio_pinctrl_ops = { >> - .get_groups_count = lpi_gpio_get_groups_count, >> - .get_group_name = lpi_gpio_get_group_name, >> - .get_group_pins = lpi_gpio_get_group_pins, >> + .get_groups_count = pinctrl_generic_get_group_count, >> + .get_group_name = pinctrl_generic_get_group_name, >> + .get_group_pins = pinctrl_generic_get_group_pins, >> .dt_node_to_map = pinconf_generic_dt_node_to_map_group, >> .dt_free_map = pinctrl_utils_free_map, >> }; >> @@ -582,6 +552,28 @@ static const struct gpio_chip lpi_gpio_template = { >> .dbg_show = lpi_gpio_dbg_show, >> }; >> >> +static int lpi_build_pin_desc_groups(struct lpi_pinctrl *pctrl) >> +{ >> + struct group_desc *lpi_groups; >> + int i; >> + >> + lpi_groups = devm_kcalloc(pctrl->dev, pctrl->data->npins, >> + sizeof(*lpi_groups), GFP_KERNEL); >> + if (!lpi_groups) >> + return -ENOMEM; >> + >> + for (i = 0; i < pctrl->data->npins; i++) { >> + const struct pinctrl_pin_desc *pin_info = pctrl->desc.pins + i; >> + struct group_desc *group = lpi_groups + i; >> + >> + group->name = pin_info->name; >> + group->pins = (int *)&pin_info->number; >> + pinctrl_generic_add_group(pctrl->ctrl, group->name, group->pins, 1, NULL); > I've not used this generic interface before, but I believe you need to > pair your add with pinctrl_generic_remove_group(), both in error paths > and driver remove. Okay. Will add pinctrl_generic_remove_group() accordingly. > > Makes me wonder about the usefulness of this, as you will end up with > a bit more code than you remove and you have the additional heap > allocation. Feels like I'm missing something... Here Heap allocation can be avoided.  will do accordingly and re post. > >> + } >> + >> + return 0; >> +} >> + >> static int lpi_pinctrl_probe(struct platform_device *pdev) >> { >> const struct lpi_pinctrl_variant_data *data; >> @@ -647,6 +639,10 @@ static int lpi_pinctrl_probe(struct platform_device *pdev) >> goto err_pinctrl; >> } >> >> + ret = lpi_build_pin_desc_groups(pctrl); >> + if (ret) >> + return ret; > A few lines up the code does error handling by goto err_pinctrl, you > should do the same. Okay. will update accordingly. > > Regards, > Bjorn > >> + >> ret = devm_gpiochip_add_data(dev, &pctrl->chip, pctrl); >> if (ret) { >> dev_err(pctrl->dev, "can't add gpio chip\n"); >> -- >> 2.7.4 >>