Received: by 2002:a05:6a10:413:0:0:0:0 with SMTP id 19csp936595pxp; Wed, 16 Mar 2022 21:55:22 -0700 (PDT) X-Google-Smtp-Source: ABdhPJycCVBbHTl27LzlyLEQt2hKFvOV3GutXbMZwoau1SLSEqeiv3tGBzQ/n537KRrPLPnLo0uV X-Received: by 2002:a17:90b:1bc1:b0:1bf:7dc6:bc78 with SMTP id oa1-20020a17090b1bc100b001bf7dc6bc78mr3296608pjb.122.1647492922132; Wed, 16 Mar 2022 21:55:22 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1647492922; cv=none; d=google.com; s=arc-20160816; b=VrDJnIQg+K7FF/jKH57c7wWt1lpGCwbmZ7/+0tpBeDn7qfZZwVAeevzLOxwIIYE+lM Y1RlXMEOZ6M0I5G3QNfclsoqHnqpV1jL+vzDkqINNTOjecoPlWOqWNl7IApWaiYv7AYy 3GB/2vOOeXuMPy683SJjB83CJrCpeqf3AbR2rJ9BfzO14sTFbyEKQQF6kzjUXxA8a6OU DLdkgLmT678rvH5SaoVMgutOfAduZCGkL0UQgDxYmzXIWJ/fN+45iPNFoYVVrX/cZgP9 r5/vA3auVqMieAotjBxOzUqGrdUQufrm+2faE3hsEMcWd8HUTPd5Pxxj7CECpSuhIiu6 w4YA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=2y31Pev9RvJ+AYi2tk5Fqr3q/lIbCqCcRZIraL6KZJU=; b=d7dPvXt4iugtxmqUy2i7dItiLFYNK+iWEUjx33S96rjLmLr3EJd4v0dJUYSGZjx8gv LWHo4Q/NejWX2Tp/RPeeM9jlVyq2STBLysYmgJex2EFSgK4AiWn7GlWhnuhKbXeX1cOK 1Zx6K1GnBh2OGjfWM+I9oTtvh91876cuA9L5uLhvtHGDp3JqE0Xt6CCZzMzE5GGTc4nR jjVaOqJU8ouluR1ZirkzsTMDOTEXk3pjOzr1lFOaMJMR45v8Hh653UyHmwc1phZEvdWp Dfb+pX+PWusalP9/cHagNZi6UKzaf+JatAWIS2QNMXe2np6h4+arqApc5O8P6oDRgxrT Laog== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcdkim header.b=bJHYitV0; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Return-Path: Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net. [2620:137:e000::1:18]) by mx.google.com with ESMTPS id 16-20020a17090a1a1000b001c638bda95bsi1301210pjk.6.2022.03.16.21.55.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 16 Mar 2022 21:55:22 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:18 as permitted sender) client-ip=2620:137:e000::1:18; Authentication-Results: mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcdkim header.b=bJHYitV0; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 534C8B6D0E; Wed, 16 Mar 2022 21:12:41 -0700 (PDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1349832AbiCOPwm (ORCPT + 99 others); Tue, 15 Mar 2022 11:52:42 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43052 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1349800AbiCOPwk (ORCPT ); Tue, 15 Mar 2022 11:52:40 -0400 Received: from alexa-out-sd-02.qualcomm.com (alexa-out-sd-02.qualcomm.com [199.106.114.39]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D9F3F54BFC; Tue, 15 Mar 2022 08:51:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1647359480; x=1678895480; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=2y31Pev9RvJ+AYi2tk5Fqr3q/lIbCqCcRZIraL6KZJU=; b=bJHYitV00NWHApQ4PBRiSE7hLpnYoRVIeDb7+dIP9QY88v7Ghpojt+78 QNALDHxm8k2pXMik4PX26a6kXS/Mo509AzFRmhuuYDtEfJTby3RlPW6cJ Z2hxpveVP+UXTWci2o4M2TSqrCkQt1Abu3jVOlez2mq1s9L3U7wmVWfpb Y=; Received: from unknown (HELO ironmsg04-sd.qualcomm.com) ([10.53.140.144]) by alexa-out-sd-02.qualcomm.com with ESMTP; 15 Mar 2022 08:51:20 -0700 X-QCInternal: smtphost Received: from nasanex01c.na.qualcomm.com ([10.47.97.222]) by ironmsg04-sd.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Mar 2022 08:51:18 -0700 Received: from nalasex01a.na.qualcomm.com (10.47.209.196) by nasanex01c.na.qualcomm.com (10.47.97.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.15; Tue, 15 Mar 2022 08:51:18 -0700 Received: from hu-srivasam-hyd.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Tue, 15 Mar 2022 08:51:11 -0700 From: Srinivasa Rao Mandadapu To: , , , , , , , , , , , , , , , , , Linus Walleij , CC: Srinivasa Rao Mandadapu , "Venkata Prasad Potturu" Subject: [PATCH v11 7/7] pinctrl: qcom: Update clock voting as optional Date: Tue, 15 Mar 2022 21:20:13 +0530 Message-ID: <1647359413-31662-8-git-send-email-quic_srivasam@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1647359413-31662-1-git-send-email-quic_srivasam@quicinc.com> References: <1647359413-31662-1-git-send-email-quic_srivasam@quicinc.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-Spam-Status: No, score=-2.0 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,RDNS_NONE,SPF_HELO_NONE,T_SCC_BODY_TEXT_LINE autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Update bulk clock voting to optional voting as ADSP bypass platform doesn't need macro and decodec clocks, as these macro and dcodec GDSC switches are maintained as power domains and operated from lpass clock drivers. Signed-off-by: Srinivasa Rao Mandadapu Co-developed-by: Venkata Prasad Potturu Signed-off-by: Venkata Prasad Potturu --- drivers/pinctrl/qcom/pinctrl-lpass-lpi.c | 12 +++++++++--- drivers/pinctrl/qcom/pinctrl-lpass-lpi.h | 1 + drivers/pinctrl/qcom/pinctrl-sc7280-lpass-lpi.c | 1 + 3 files changed, 11 insertions(+), 3 deletions(-) diff --git a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c index 0216ca1..3fc473a 100644 --- a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c +++ b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c @@ -401,9 +401,15 @@ int lpi_pinctrl_probe(struct platform_device *pdev) return dev_err_probe(dev, PTR_ERR(pctrl->slew_base), "Slew resource not provided\n"); - ret = devm_clk_bulk_get(dev, MAX_LPI_NUM_CLKS, pctrl->clks); - if (ret) - return dev_err_probe(dev, ret, "Can't get clocks\n"); + if (data->is_clk_optional) { + ret = devm_clk_bulk_get_optional(dev, MAX_LPI_NUM_CLKS, pctrl->clks); + if (ret) + return dev_err_probe(dev, ret, "Can't get clocks\n"); + } else { + ret = devm_clk_bulk_get(dev, MAX_LPI_NUM_CLKS, pctrl->clks); + if (ret) + return dev_err_probe(dev, ret, "Can't get clocks\n"); + } ret = clk_bulk_prepare_enable(MAX_LPI_NUM_CLKS, pctrl->clks); if (ret) diff --git a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.h b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.h index afbac2a..3bcede6 100644 --- a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.h +++ b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.h @@ -77,6 +77,7 @@ struct lpi_pinctrl_variant_data { int ngroups; const struct lpi_function *functions; int nfunctions; + int is_clk_optional; }; int lpi_pinctrl_probe(struct platform_device *pdev); diff --git a/drivers/pinctrl/qcom/pinctrl-sc7280-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-sc7280-lpass-lpi.c index d67ff25..304d8a2 100644 --- a/drivers/pinctrl/qcom/pinctrl-sc7280-lpass-lpi.c +++ b/drivers/pinctrl/qcom/pinctrl-sc7280-lpass-lpi.c @@ -142,6 +142,7 @@ static const struct lpi_pinctrl_variant_data sc7280_lpi_data = { .ngroups = ARRAY_SIZE(sc7280_groups), .functions = sc7280_functions, .nfunctions = ARRAY_SIZE(sc7280_functions), + .is_clk_optional = 1, }; static const struct of_device_id lpi_pinctrl_of_match[] = { -- 2.7.4