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[23.128.96.19]) by mx.google.com with ESMTPS id w12-20020a170902e88c00b00153db4c8ccesi2047165plg.62.2022.03.16.22.24.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 16 Mar 2022 22:24:40 -0700 (PDT) Received-SPF: softfail (google.com: domain of transitioning linux-kernel-owner@vger.kernel.org does not designate 23.128.96.19 as permitted sender) client-ip=23.128.96.19; Authentication-Results: mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcdkim header.b=dP1FW+Al; spf=softfail (google.com: domain of transitioning linux-kernel-owner@vger.kernel.org does not designate 23.128.96.19 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 2738EEF0AF; Wed, 16 Mar 2022 21:31:46 -0700 (PDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1353914AbiCPGTW (ORCPT + 99 others); Wed, 16 Mar 2022 02:19:22 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49288 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1353871AbiCPGTH (ORCPT ); Wed, 16 Mar 2022 02:19:07 -0400 Received: from alexa-out.qualcomm.com (alexa-out.qualcomm.com [129.46.98.28]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CC2A6E97; Tue, 15 Mar 2022 23:17:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1647411470; x=1678947470; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=GUK4JIE654NZxV1pFo5SaB16H7zXCfmo7RTrkPYh/S0=; b=dP1FW+AlJ3T0n9Q7JUc8gnMYGyZC9v58iKFX6dFSbdOqj1PZD45qFfdx CqfEnJuEdKZ4KaObjcDbElRIeTRQqNUV74VwEqKKkM6GiHEIaidZJHBOy LygJiGRf1XB1ooSL4yGc4rRy8IWYfkpNuyEOAPYhEx7t+0j6Morfu8ZzR M=; Received: from ironmsg07-lv.qualcomm.com ([10.47.202.151]) by alexa-out.qualcomm.com with ESMTP; 15 Mar 2022 23:17:50 -0700 X-QCInternal: smtphost Received: from ironmsg02-blr.qualcomm.com ([10.86.208.131]) by ironmsg07-lv.qualcomm.com with ESMTP/TLS/AES256-SHA; 15 Mar 2022 23:17:48 -0700 X-QCInternal: smtphost Received: from hu-rohiagar-hyd.qualcomm.com (HELO hu-sgudaval-hyd.qualcomm.com) ([10.213.106.138]) by ironmsg02-blr.qualcomm.com with ESMTP; 16 Mar 2022 11:47:37 +0530 Received: by hu-sgudaval-hyd.qualcomm.com (Postfix, from userid 3970568) id 8CB5F478E; Wed, 16 Mar 2022 11:47:36 +0530 (+0530) From: Rohit Agarwal To: agross@kernel.org, bjorn.andersson@linaro.org, robh+dt@kernel.org Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Rohit Agarwal Subject: [PATCH 5/6] ARM: dts: qcom: Add PMIC pmx65 dts Date: Wed, 16 Mar 2022 11:47:26 +0530 Message-Id: <1647411447-25249-6-git-send-email-quic_rohiagar@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1647411447-25249-1-git-send-email-quic_rohiagar@quicinc.com> References: <1647411447-25249-1-git-send-email-quic_rohiagar@quicinc.com> X-Spam-Status: No, score=-2.0 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,RDNS_NONE,SPF_HELO_NONE,T_SCC_BODY_TEXT_LINE autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add DTS for PMIC PMX65 found in Qualcomm platforms. Signed-off-by: Rohit Agarwal --- arch/arm/boot/dts/qcom-pmx65.dtsi | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) create mode 100644 arch/arm/boot/dts/qcom-pmx65.dtsi diff --git a/arch/arm/boot/dts/qcom-pmx65.dtsi b/arch/arm/boot/dts/qcom-pmx65.dtsi new file mode 100644 index 0000000..5411b83 --- /dev/null +++ b/arch/arm/boot/dts/qcom-pmx65.dtsi @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include + +&spmi_bus { + pmic@1 { + compatible = "qcom,pmx65", "qcom,spmi-pmic"; + reg = <1 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pmx65_temp: temp-alarm@a00 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0xa00>; + interrupts = <0x1 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells = <0>; + }; + + pmx65_gpios: pinctrl@8800 { + compatible = "qcom,pmx65-gpio"; + reg = <0x8800>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; +}; -- 2.7.4