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Message-ID: <312d724c-e43f-d766-49fb-9c5b10fe8b07@intel.com>
Date:   Wed, 16 Mar 2022 13:28:07 +0200
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Subject: Re: [PATCH] mmc: block: enable cache-flushing when mmc cache is on
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To:     Avri Altman <Avri.Altman@wdc.com>,
        Michael Wu <michael@allwinnertech.com>,
        "ulf.hansson@linaro.org" <ulf.hansson@linaro.org>,
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From:   Adrian Hunter <adrian.hunter@intel.com>
Organization: Intel Finland Oy, Registered Address: PL 281, 00181 Helsinki,
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On 16.3.2022 13.09, Avri Altman wrote:
>> Hi Avril & Adrian,
>> Thanks for your efforts. Could we have an agreement now --
>>
>> 1. enabling-cache and cmd23/reliable-write should be independent;
>>
>> Here's what I found in the spec JESD84-B51:
>>  > 6.6.31 Cache
>>  > Caching of data shall apply only for the single block
>>  > read/write(CMD17/24), pre-defined multiple block
>>  > read/write(CMD23+CMD18/25) and open ended multiple block
>>  > read/write(CMD18/25+CMD12) commands and excludes any other access
>>  > e.g., to the register space(e.g., CMD6).
>> Which means with CMD18/25+CMD12 (without using CMD23), the cache can
>> also be enabled. Maybe this could be an evidence of the independence
>> between enabling-cache and cmd23/reliable-write?
> Acked-by: Avri Altman <avri.altman@wdc.com>
> 
> Thanks,
> Avri
> 
>>
>> 2. We don't consider supporting SD in this change.
>>
>>  > On 14/03/2022 19:10, Avri Altman wrote:
>>  >> Here is what our SD system guys wrote:
>>  >> " In SD we don’t support reliable write and this eMMC driver may not
>>  >>    be utilizing the cache feature we added in SD5.0.
>>  >>   The method of cache flush is different between SD and eMMC."
>>  >>
>>  >> So adding SD seems to be out of scope of this change.
>>
>> Is there anything else I can do about this patch? Thanks again.

So we are not going to let the block layer know about SD cache?
Or is it a separate change?