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Subject: Re: [PATCH 11/16] clk: qcom: krait-cc: force sec_mux to QSB
From:   Stephen Boyd <sboyd@kernel.org>
To:     Andy Gross <agross@kernel.org>,
        Ansuel Smith <ansuelsmth@gmail.com>,
        Bjorn Andersson <bjorn.andersson@linaro.org>,
        Jonathan Hunter <jonathanh@nvidia.com>,
        Michael Turquette <mturquette@baylibre.com>,
        Peter De Schrijver <pdeschrijver@nvidia.com>,
        Prashant Gaikwad <pgaikwad@nvidia.com>,
        Rob Herring <robh+dt@kernel.org>,
        Thierry Reding <thierry.reding@gmail.com>,
        devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org,
        linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org,
        linux-tegra@vger.kernel.org
Date:   Tue, 15 Mar 2022 15:47:02 -0700
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Message-Id: <20220315224703.EE7E8C340E8@smtp.kernel.org>
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Quoting Ansuel Smith (2022-03-13 12:04:14)
> Now that we have converted every driver to parent_data, it was
> notice that the bootloader can't really leave the system in a
> strange state where l2 or the cpu0/1 can be sourced in a number of ways
> for example cpu1 sourcing out of qsb, l2 sourcing out of pxo.
> To correctly reset the mux and the HFPLL force the sec_mux to QSB.
>=20
> Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
> ---
>  drivers/clk/qcom/krait-cc.c | 12 ++++++++++--
>  1 file changed, 10 insertions(+), 2 deletions(-)
>=20
> diff --git a/drivers/clk/qcom/krait-cc.c b/drivers/clk/qcom/krait-cc.c
> index 6530f10a546f..1bdc89c097e6 100644
> --- a/drivers/clk/qcom/krait-cc.c
> +++ b/drivers/clk/qcom/krait-cc.c
> @@ -15,6 +15,8 @@
> =20
>  #include "clk-krait.h"
> =20
> +#define QSB_RATE       1
> +
>  static unsigned int sec_mux_map[] =3D {
>         2,
>         0,
> @@ -178,6 +180,12 @@ krait_add_sec_mux(struct device *dev, struct clk *qs=
b, int id,
>         if (ret)
>                 clk =3D ERR_PTR(ret);
> =20
> +       /* Force the sec_mux to be set to QSB rate.

The comment start should be on a line alone

	/*
	 * Force the ...

> +        * This is needed to correctly set the parents and
> +        * to later reset mux and HFPLL to a known freq.
> +        */
> +       clk_set_rate(clk, QSB_RATE);
> +
>  err_clk:
>         if (unique_aux)
>                 kfree(parent_name);