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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: BN9PR11MB5276.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 130de06b-a1a5-4763-05f1-08da0679ed85 X-MS-Exchange-CrossTenant-originalarrivaltime: 15 Mar 2022 11:49:57.0667 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: PBIozWutrrfJlI7DGXGV9KQK/r1CjQX3DiTVd6bUSsSxdMdNZfUVwEzraaDowin36x++Z+an+EY0pnP4vghMDQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: BYAPR11MB2805 X-OriginatorOrg: intel.com X-Spam-Status: No, score=-3.5 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,RDNS_NONE,SPF_HELO_NONE,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org > From: Jean-Philippe Brucker > Sent: Tuesday, March 15, 2022 7:27 PM >=20 > On Mon, Mar 14, 2022 at 10:07:06PM -0700, Jacob Pan wrote: > > From: Lu Baolu > > > > An IOMMU domain represents an address space which can be attached by > > devices that perform DMA within a domain. However, for platforms with > > PASID capability the domain attachment needs be handled at device+PASID > > level. There can be multiple PASIDs within a device and multiple device= s > > attached to a given domain. > > This patch introduces a new IOMMU op which support device, PASID, and > > IOMMU domain attachment. The immediate use case is for PASID capable > > devices to perform DMA under DMA APIs. > > > > Signed-off-by: Lu Baolu > > Signed-off-by: Jacob Pan > > --- > > include/linux/iommu.h | 6 ++++++ > > 1 file changed, 6 insertions(+) > > > > diff --git a/include/linux/iommu.h b/include/linux/iommu.h > > index 369f05c2a4e2..fde5b933dbe3 100644 > > --- a/include/linux/iommu.h > > +++ b/include/linux/iommu.h > > @@ -227,6 +227,8 @@ struct iommu_iotlb_gather { > > * @aux_get_pasid: get the pasid given an aux-domain > > * @sva_bind: Bind process address space to device > > * @sva_unbind: Unbind process address space from device > > + * @attach_dev_pasid: attach an iommu domain to a pasid of device > > + * @detach_dev_pasid: detach an iommu domain from a pasid of device >=20 > Isn't that operation "assign a PASID to a domain" instead? In patch 5, > the domain is already attached to the device, so set_domain_pasid() might > be clearer and to the point. If the IOMMU driver did the allocation we > could also avoid patch 1. iiuc this API can also work for future SIOV usage where each mdev attached to the domain has its own pasid. "assigning a PASID to a domain" sounds like going back to the previous aux domain approach which has one PASID per domain and that PASID is used on all devices attached to the aux domain= ... >=20 > If I understand correctly this series is not about a generic PASID API > that allows drivers to manage multiple DMA address spaces, because there > still doesn't seem to be any interest in that. It's about the specific > IDXD use-case, so let's focus on that. We can introduce a specialized cal= l > such as (iommu|dma)_set_device_pasid(), which will be easy to consolidate > later into a more generic "dma_enable_pasid()" API if that ever seems > useful. >=20 > Thanks, > Jean >=20 > > * @sva_get_pasid: Get PASID associated to a SVA handle > > * @page_response: handle page request response > > * @cache_invalidate: invalidate translation caches > > @@ -296,6 +298,10 @@ struct iommu_ops { > > struct iommu_sva *(*sva_bind)(struct device *dev, struct mm_struct > *mm, > > void *drvdata); > > void (*sva_unbind)(struct iommu_sva *handle); > > + int (*attach_dev_pasid)(struct iommu_domain *domain, > > + struct device *dev, ioasid_t id); > > + void (*detach_dev_pasid)(struct iommu_domain *domain, > > + struct device *dev, ioasid_t id); > > u32 (*sva_get_pasid)(struct iommu_sva *handle); > > > > int (*page_response)(struct device *dev, > > -- > > 2.25.1 > >