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Thu, 17 Mar 2022 01:30:38 -0500 From: Sandipan Das To: , , CC: , , , , , , , , , , , , , , , , , Subject: [PATCH 6/7] perf/x86/amd/core: Add PerfMonV2 overflow handling Date: Thu, 17 Mar 2022 11:58:35 +0530 Message-ID: <7d43b4ba8a7c3c0833495f3fabfcfc6df8db3732.1647498015.git.sandipan.das@amd.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 08000805-ebfa-43ab-7a31-08da07dfaa66 X-MS-TrafficTypeDiagnostic: CY4PR12MB1464:EE_ X-Microsoft-Antispam-PRVS: X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: cePuP8xUAXhZYw6vkzwJSp+oNk2WEAz7TDQ2dUzbOzBI/Z4f3byA7GHoEIiU0fOplgTMZfcMEan9nw43wP2aG9K96l1c3omLnSTgwK36oWj/uJ1jMoJcn+XwuHEwM6p6N4VaGK4zyeyOi0tA0pt9zUHGzI4JwFZgJrtu4rQ2B5JdVg9IpXkpybOboMqggyU5szXKipKcCMQKHDQZUpTB/CghB2JKjmso8Vc7X8cRZPp7i+Bl3sGZ8j7JJgT7fqlBAQnlJa2CJbj4FE3D0fk42MQJQkto6RasPbVTZa/rsp2vnP4O5S+6SEO07qFnu0aUSVFvTyDUztG9CyH7UUcq0wZJAUQSvNjDH4Ph3Z/ah3hQM3GNE5MQqRLccXvjYhJOaODP6AUhqnV8CnF+dGFtRHy2RAMwZzbIqc6t1MgG2F3tm3YCDDfQHi/2HVHEr4Sj5Ej1ULD/LmpT3n1BNmSN64B0C7obesNpM92swGOAeGarVlQ8jvcvMUXAtCX7Eio9eG8xVkj6UrsAcZf/ZrBimjg2AFI9pMf9Q+tEnpHsCmZ6Q4mM9rawXlNYTkaqLt9JcT2PzJ61OY6VZjmfpYRlh83BgZcZQuiBYf+OyrWvmDX9Sa9S9RBo9hg9e2CMiiefi70XxJ4s6gQ0To6TAIm8PTTe9/QMAXX1gSq8QSy8GBWhc7cBbqbncJhty6HaLul9Qwtb/smZuQBLba7GzLJILQ== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230001)(4636009)(46966006)(40470700004)(36840700001)(44832011)(36860700001)(40460700003)(36756003)(316002)(4326008)(70206006)(8676002)(5660300002)(70586007)(54906003)(110136005)(7416002)(8936002)(83380400001)(82310400004)(426003)(336012)(6666004)(356005)(81166007)(186003)(26005)(16526019)(47076005)(508600001)(86362001)(2906002)(7696005)(2616005)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Mar 2022 06:30:44.3197 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 08000805-ebfa-43ab-7a31-08da07dfaa66 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT053.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY4PR12MB1464 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org If AMD Performance Monitoring Version 2 (PerfMonV2) is supported, use a new scheme to process Core PMC overflows in the NMI handler using the new global control and status registers. This will be bypassed on unsupported hardware (x86_pmu.version < 2). In x86_pmu_handle_irq(), overflows are detected by testing the contents of the PERF_CTR register for each active PMC in a loop. The new scheme instead inspects the overflow bits of the global status register. The Performance Counter Global Status (PerfCntrGlobalStatus) register has overflow (PerfCntrOvfl) bits for each PMC. This is, however, a read-only MSR. To acknowledge that overflows have been processed, the NMI handler must clear the bits by writing to the PerfCntrGlobalStatusClr register. In x86_pmu_handle_irq(), PMCs counting the same event that are started and stopped at the same time record slightly different counts due to delays in between reads from the PERF_CTR registers. This is fixed by stopping and starting the PMCs at the same before and with a single write to the Performance Counter Global Control (PerfCntrGlobalCtl) upon entering and before exiting the NMI handler. Signed-off-by: Sandipan Das --- arch/x86/events/amd/core.c | 125 +++++++++++++++++++++++++++++++++++-- 1 file changed, 121 insertions(+), 4 deletions(-) diff --git a/arch/x86/events/amd/core.c b/arch/x86/events/amd/core.c index 532e9bd76bf1..fbbba981d0bd 100644 --- a/arch/x86/events/amd/core.c +++ b/arch/x86/events/amd/core.c @@ -7,6 +7,7 @@ #include #include #include +#include #include #include "../perf_event.h" @@ -601,6 +602,45 @@ static inline void amd_pmu_set_global_ctl(u64 ctl) wrmsrl(MSR_AMD64_PERF_CNTR_GLOBAL_CTL, ctl); } +static inline u64 amd_pmu_get_global_overflow(void) +{ + u64 status; + + /* PerfCntrGlobalStatus is read-only */ + rdmsrl(MSR_AMD64_PERF_CNTR_GLOBAL_STATUS, status); + + return status & amd_pmu_global_cntr_mask; +} + +static inline void amd_pmu_ack_global_overflow(u64 status) +{ + /* + * PerfCntrGlobalStatus is read-only but an overflow acknowledgment + * mechanism exists; writing 1 to a bit in PerfCntrGlobalStatusClr + * clears the same bit in PerfCntrGlobalStatus + */ + + /* Only allow modifications to PerfCntrGlobalStatus.PerfCntrOvfl */ + status &= amd_pmu_global_cntr_mask; + wrmsrl(MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_CLR, status); +} + +static bool amd_pmu_legacy_has_overflow(int idx) +{ + u64 counter; + + rdmsrl(x86_pmu_event_addr(idx), counter); + + return !(counter & BIT_ULL(x86_pmu.cntval_bits - 1)); +} + +static bool amd_pmu_global_has_overflow(int idx) +{ + return amd_pmu_get_global_overflow() & BIT_ULL(idx); +} + +DEFINE_STATIC_CALL(amd_pmu_has_overflow, amd_pmu_legacy_has_overflow); + /* * When a PMC counter overflows, an NMI is used to process the event and * reset the counter. NMI latency can result in the counter being updated @@ -613,7 +653,6 @@ static inline void amd_pmu_set_global_ctl(u64 ctl) static void amd_pmu_wait_on_overflow(int idx) { unsigned int i; - u64 counter; /* * Wait for the counter to be reset if it has overflowed. This loop @@ -621,8 +660,7 @@ static void amd_pmu_wait_on_overflow(int idx) * forever... */ for (i = 0; i < OVERFLOW_WAIT_COUNT; i++) { - rdmsrl(x86_pmu_event_addr(idx), counter); - if (counter & (1ULL << (x86_pmu.cntval_bits - 1))) + if (!static_call(amd_pmu_has_overflow)(idx)) break; /* Might be in IRQ context, so can't sleep */ @@ -718,6 +756,83 @@ static void amd_pmu_enable_event(struct perf_event *event) static_call(amd_pmu_enable_event)(event); } +static int amd_pmu_global_handle_irq(struct pt_regs *regs) +{ + struct perf_sample_data data; + struct cpu_hw_events *cpuc; + struct hw_perf_event *hwc; + struct perf_event *event; + u64 val, status, mask; + int handled = 0, idx; + + status = amd_pmu_get_global_overflow(); + + /* Check if any overflows are pending */ + if (!status) + return 0; + + /* Stop counting */ + amd_pmu_global_disable_all(); + + cpuc = this_cpu_ptr(&cpu_hw_events); + + /* + * Some chipsets need to unmask the LVTPC in a particular spot + * inside the nmi handler. As a result, the unmasking was + * pushed into all the nmi handlers. + * + * This generic handler doesn't seem to have any issues where + * the unmasking occurs so it was left at the top. + * + * N.B. Taken from x86_pmu_handle_irq() + */ + apic_write(APIC_LVTPC, APIC_DM_NMI); + + for (idx = 0; idx < x86_pmu.num_counters; idx++) { + if (!test_bit(idx, cpuc->active_mask)) + continue; + + event = cpuc->events[idx]; + hwc = &event->hw; + val = x86_perf_event_update(event); + mask = BIT_ULL(idx); + + if (!(status & mask)) + continue; + + /* Event overflow */ + handled++; + perf_sample_data_init(&data, 0, hwc->last_period); + + if (!x86_perf_event_set_period(event)) + continue; + + if (perf_event_overflow(event, &data, regs)) + x86_pmu_stop(event, 0); + + status &= ~mask; + } + + /* + * It should never be the case that some overflows are not handled as + * the corresponding PMCs are expected to be inactive according to the + * active_mask + */ + WARN_ON(status > 0); + + /* Clear overflow bits */ + amd_pmu_ack_global_overflow(~status); + + inc_irq_stat(apic_perf_irqs); + + /* Resume counting */ + amd_pmu_global_enable_all(0); + + return handled; +} + +DEFINE_STATIC_CALL(amd_pmu_handle_irq, x86_pmu_handle_irq); + /* * Because of NMI latency, if multiple PMC counters are active or other sources * of NMIs are received, the perf NMI handler can handle one or more overflowed @@ -741,7 +856,7 @@ static int amd_pmu_handle_irq(struct pt_regs *regs) int handled; /* Process any counter overflows */ - handled = x86_pmu_handle_irq(regs); + handled = static_call(amd_pmu_handle_irq)(regs); /* * If a counter was handled, record a timestamp such that un-handled @@ -1041,6 +1156,8 @@ static int __init amd_core_pmu_init(void) static_call_update(amd_pmu_enable_all, amd_pmu_global_enable_all); static_call_update(amd_pmu_disable_all, amd_pmu_global_disable_all); static_call_update(amd_pmu_enable_event, amd_pmu_global_enable_event); + static_call_update(amd_pmu_has_overflow, amd_pmu_global_has_overflow); + static_call_update(amd_pmu_handle_irq, amd_pmu_global_handle_irq); } /* -- 2.32.0