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 <CAHp75Vc+uSNF4L0WCfCyadOqJ6szXS3Ct5BmEUbeQ_aKg1zjWg@mail.gmail.com> <87wngtx79f.wl-maz@kernel.org>
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From:   "Lad, Prabhakar" <prabhakar.csengg@gmail.com>
Date:   Thu, 17 Mar 2022 11:59:52 +0000
Message-ID: <CA+V-a8uBrau7-0x95O750nPeckz=vdhK2RJtFZ2rfiQhEtrdwA@mail.gmail.com>
Subject: Re: [RFC PATCH v4 0/5] Renesas RZ/G2L IRQC support
To:     Marc Zyngier <maz@kernel.org>
Cc:     Andy Shevchenko <andy.shevchenko@gmail.com>,
        Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>,
        Thomas Gleixner <tglx@linutronix.de>,
        Rob Herring <robh+dt@kernel.org>,
        Linus Walleij <linus.walleij@linaro.org>,
        Bartosz Golaszewski <brgl@bgdev.pl>,
        Geert Uytterhoeven <geert+renesas@glider.be>,
        Philipp Zabel <p.zabel@pengutronix.de>,
        Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
        devicetree <devicetree@vger.kernel.org>,
        "open list:GPIO SUBSYSTEM" <linux-gpio@vger.kernel.org>,
        Linux-Renesas <linux-renesas-soc@vger.kernel.org>,
        Biju Das <biju.das.jz@bp.renesas.com>
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Hi Marc,

On Thu, Mar 17, 2022 at 9:23 AM Marc Zyngier <maz@kernel.org> wrote:
>
> On Thu, 17 Mar 2022 08:46:14 +0000,
> Andy Shevchenko <andy.shevchenko@gmail.com> wrote:
> >
> > On Thu, Mar 17, 2022 at 5:43 AM Lad Prabhakar
> > <prabhakar.mahadev-lad.rj@bp.renesas.com> wrote:
> > >
> > > Hi All,
> > >
> > > The RZ/G2L Interrupt Controller is a front-end for the GIC found on
> > > Renesas RZ/G2L SoC's with below pins:
> > > - IRQ sense select for 8 external interrupts, mapped to 8 GIC SPI interrupts
> > > - GPIO pins used as external interrupt input pins out of GPIOINT0-122 a
> > >   maximum of only 32 can be mapped to 32 GIC SPI interrupts,
> > > - NMI edge select.
> > >
> > What I want to know now is whether it is going to collide with Marc's
> > series about GPIO IRQ chip constification?
>
> Probably, but the current scheme will still be alive for some time
> (you'll need a couple of cycles to sort out all the drivers).
>
Ouch, thanks for letting me know. BTW there are a couple of changes to
GPIO core which you have to review (this was missed in the previous
version).

Cheers,
Prabhakar

> Worse case, this can be fixed at merge time.
>
>         M.
>
> --
> Without deviation from the norm, progress is not possible.