Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:18 as permitted sender) client-ip=2620:137:e000::1:18;
Message-ID: <7032fbfb-8899-d00b-a7fa-811e19d38ce2@nvidia.com>
Date:   Thu, 17 Mar 2022 15:26:28 +0000
User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101
 Thunderbird/91.5.0
Subject: Re: [PATCH 2/3] spi: tegra210-quad: Add wait polling support
Content-Language: en-US
From:   Jon Hunter <jonathanh@nvidia.com>
To:     Krishna Yarlagadda <kyarlagadda@nvidia.com>,
        "broonie@kernel.org" <broonie@kernel.org>,
        "thierry.reding@gmail.com" <thierry.reding@gmail.com>,
        "linux-spi@vger.kernel.org" <linux-spi@vger.kernel.org>,
        "linux-tegra@vger.kernel.org" <linux-tegra@vger.kernel.org>,
        Ashish Singhal <ashishsingha@nvidia.com>
Cc:     Sowjanya Komatineni <skomatineni@nvidia.com>,
        Laxman Dewangan <ldewangan@nvidia.com>,
        "robh+dt@kernel.org" <robh+dt@kernel.org>,
        "devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
References: <20220317012006.15080-1-kyarlagadda@nvidia.com>
 <20220317012006.15080-3-kyarlagadda@nvidia.com>
 <391736bc-84c2-ec8b-9f04-614365953da3@nvidia.com>
 <DM4PR12MB57692EB17ABCA36E0515412EC3129@DM4PR12MB5769.namprd12.prod.outlook.com>
 <edcae0c1-a576-1560-5ecb-9dcf08d8ead3@nvidia.com>
In-Reply-To: <edcae0c1-a576-1560-5ecb-9dcf08d8ead3@nvidia.com>
Content-Type: text/plain; charset=UTF-8; format=flowed
Content-Transfer-Encoding: 8bit
MIME-Version: 1.0
X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1
X-MS-Exchange-AntiSpam-MessageData-0: =?utf-8?B?eFhKeC8zWFFqYm1QdjZsUXUvZ2R6TjV1OGpDNzJtbXJHR2NwOFh0bmFuMVoy?=
 =?utf-8?B?M29hNE5jazZ2YjdpYTBhVDIxYlpoUVh0M3NBcFZzTHdPOFQ5dnJBTXpOZDhM?=
 =?utf-8?B?ZUVTckZ2MlkrSHpoWk1yU1BDWmlZU3VMQVZWNnpVMEJoQWYwZklWUWlIaUhj?=
 =?utf-8?B?SUo3T2xqdlJRRm54VFROd3MwYnk2M1VKL3NFaWNKS3Q2NE1KNGkwNlRuci9s?=
 =?utf-8?B?YWhJOFpjUjVzbVJjYTd1VWFDMll2Sm1IRkFxWUh1K0R1dldubUI5ZVlkUVlR?=
 =?utf-8?B?NEE0OEwwZW5qakxlelA5OHZSamh1Y3BTNC9ucTFxRUoyWHdHbGhXV2NrUzFt?=
 =?utf-8?B?ZW5iQUNORW1OeXNsU0UzTGc2dGFhSEl3QzhxblJ2bHpScGp1cjVnMHVBT0d3?=
 =?utf-8?B?TnFrN043UmJOaUFrRm85T254Ri9Uc2t6RE9QTFR6TTMvdHEwUHh2VEFmYUZP?=
 =?utf-8?B?T0orb0ljL2tCeFN6b1VZMGJLUHR4azY2a0k3Qk9MN09GZFRQREZsVHBCbmpE?=
 =?utf-8?B?MGRkdjU3M1BVOWxBbFlWb2VYeG5sdGt0ZXNlU0kvb3BrRmdVQXBTVFl0Mlhs?=
 =?utf-8?B?OEF2bHlWNTlCL1Jsb0dVN0pXc1N4UnNiYUFIKzV0L1BjL1phcDZ5RFprTXVU?=
 =?utf-8?B?bnpYYnRXdjR2ZUNUeG9rLzBUTUxOWmpOMlRzRURCQ28rd3lqUnQ2d0RreHNH?=
 =?utf-8?B?dkpTN1NNclBGbW1CSUE5NUFOSUMwODFKMjVTcnNXYkJHWktTK2xhK1c3UGVh?=
 =?utf-8?B?RHY2OXFrYVJodGNFZTdHNi9IalJtbzRPbEV3N3A1VUtFOEMybkU5TTErQndT?=
 =?utf-8?B?VzNuSlM4V3FzYTg3aHNvQWJ4MDFqcndiZG1PUmVWb2pRWUNQelo0MmUyeHhC?=
 =?utf-8?B?RU9wRHhmUTNUc3NOMTlVRkYrMnRHVE5sZmNHYzNDSWhuOUFkOWE3M0FvSTA1?=
 =?utf-8?B?TGpVMDNxSWpyb1pFT1Q1V2h5VmVQQVFUUWZMbEU5dm5tdVFJbXllWldpYmtQ?=
 =?utf-8?B?bituQTlybGFPa2xmS25PSmFTYUs4UE5SYk43ZDZ0SlAvdUF4aDZXdjlEQVRM?=
 =?utf-8?B?aW9leExTUnZtS1AwUXJBTTVsaTkxTTBKQmIvSkF3dUMyVU5DcENtdUw5aWpL?=
 =?utf-8?B?VEN3bUVva0czd0hHWktENDh2T3E0VmkvRGtXdzhWT1N2NlMyNEJHbkJoaVdh?=
 =?utf-8?B?Vm51b2ZyWXIralBiS2x1d2NBTGp5NzN3R29aSlhRVTBLOWhsZFNpTmJUMlMv?=
 =?utf-8?B?SGVuQ1FlbDVueFVoOEYzRXZkWFNBRFc5cDFJbWZzUzFnK2toNXFyRm5icjhO?=
 =?utf-8?B?bGE1OFg4MGJFWmwvMyszbUtJWFE5MFA2U0EybFVXcDBiRzhPbjhOcWliQ2xN?=
 =?utf-8?B?SjdnSXYxTjVHVDdQNzc2Z1RCOFc4ZlM4dXMwTnl4UXdHWUVPcUx0cnFiZmRF?=
 =?utf-8?B?UWhWMVF2ZUZSeUJ4NjFvWlRFb0E1bzN4VzFMU0xmczYyMWIxdTFwUysvZloy?=
 =?utf-8?B?aVl1SEZNb3dicmlvQ2RqdG85endDTnJWQ2wvaUdwcE5lbENwOXpMQjJSVTRQ?=
 =?utf-8?B?NnZsZkdGbE5vK2h6MlZ5UDBSdDFvNWtBeHNERVZGMGlTNU5wVk9QbGp2WVV4?=
 =?utf-8?B?RHhIaldKckhxUjBZRjByTkU1RVJiZ3VIZURRbGJtQXB2TjV4U29xUnJGTjFP?=
 =?utf-8?B?OFRKbFdwZzB3cSs1K1ZwNnk2bmFvaWpqRlIrbll4Yy9nMDM2UTg2UllodVN4?=
 =?utf-8?B?VUVrWFdmNFlVRUVoSnY1aTdXR25yTFA4em5FeEdES3VaZThUbUVQcVdhRy9K?=
 =?utf-8?B?K0VCTmp1V29hOHhxY3UvYmo4UEh0UDd2S0ZuOVdWRE1oSUxVcUM0OHd5Z09J?=
 =?utf-8?B?Sk9lRk9tSHBJNHI5UXNLVzdrQmRodEJ3L05obk9DRFVCZ2trYkR3aG9tY0ha?=
 =?utf-8?B?YmhMMnRFalliYWd3OHNxeFRtNU1kZjlMekI3TFovZWIxN2RMUVUyL2JWSTJS?=
 =?utf-8?B?b1RvZ0JRbW9BPT0=?=
X-OriginatorOrg: Nvidia.com
X-MS-Exchange-CrossTenant-Network-Message-Id: 65f99f77-5357-4f16-45c3-08da082a85ef
X-MS-Exchange-CrossTenant-AuthSource: CO6PR12MB5444.namprd12.prod.outlook.com
X-MS-Exchange-CrossTenant-AuthAs: Internal
X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Mar 2022 15:26:35.8170
 (UTC)
X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted
X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a
X-MS-Exchange-CrossTenant-MailboxType: HOSTED
X-MS-Exchange-CrossTenant-UserPrincipalName: 9DKqFmTKinnAKnmyWzYCDm5TEaU+cAT5bdQrvUv6/6LC7+Gne8LY4QugkPDvoDBEK3TQCcHP0uFAnHs9os7ChQ==
X-MS-Exchange-Transport-CrossTenantHeadersStamped: MWHPR12MB1312
X-Spam-Status: No, score=-3.5 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH,
	DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,
	MAILING_LIST_MULTI,NICE_REPLY_A,RDNS_NONE,SPF_HELO_NONE,
	T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no
	version=3.4.6
X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on
	lindbergh.monkeyblade.net
Precedence: bulk
List-ID: <linux-kernel.vger.kernel.org>
X-Mailing-List: linux-kernel@vger.kernel.org


On 17/03/2022 09:44, Jon Hunter wrote:
> 
> On 17/03/2022 09:02, Krishna Yarlagadda wrote:
>>> -----Original Message-----
>>> From: Jonathan Hunter <jonathanh@nvidia.com>
>>> Sent: 17 March 2022 14:25
>>> To: Krishna Yarlagadda <kyarlagadda@nvidia.com>; broonie@kernel.org; 
>>> thierry.reding@gmail.com; linux-spi@vger.kernel.org; linux-
>>> tegra@vger.kernel.org; Ashish Singhal <ashishsingha@nvidia.com>
>>> Cc: Sowjanya Komatineni <skomatineni@nvidia.com>; Laxman Dewangan 
>>> <ldewangan@nvidia.com>; robh+dt@kernel.org;
>>> devicetree@vger.kernel.org; linux-kernel@vger.kernel.org
>>> Subject: Re: [PATCH 2/3] spi: tegra210-quad: Add wait polling support
>>>
>>>
>>> On 17/03/2022 01:20, Krishna Yarlagadda wrote:
>>>> Controller can poll for wait state inserted by TPM device and
>>>> handle it.
>>>>
>>>> Signed-off-by: Krishna Yarlagadda <kyarlagadda@nvidia.com>
>>>> ---
>>>>    drivers/spi/spi-tegra210-quad.c | 31 +++++++++++++++++++++++++++++++
>>>>    1 file changed, 31 insertions(+)
>>>>
>>>> diff --git a/drivers/spi/spi-tegra210-quad.c 
>>>> b/drivers/spi/spi-tegra210-quad.c
>>>> index a2e225e8f7f0..ecf171bfcdce 100644
>>>> --- a/drivers/spi/spi-tegra210-quad.c
>>>> +++ b/drivers/spi/spi-tegra210-quad.c
>>>> @@ -142,6 +142,7 @@
>>>>
>>>>    #define QSPI_GLOBAL_CONFIG            0X1a4
>>>>    #define QSPI_CMB_SEQ_EN                BIT(0)
>>>> +#define QSPI_TPM_WAIT_POLL_EN            BIT(1)
>>>>
>>>>    #define QSPI_CMB_SEQ_ADDR            0x1a8
>>>>    #define QSPI_ADDRESS_VALUE_SET(X)        (((x) & 0xFFFF) << 0)
>>>> @@ -165,11 +166,13 @@ struct tegra_qspi_soc_data {
>>>>        bool has_dma;
>>>>        bool cmb_xfer_capable;
>>>>        bool cs_count;
>>>> +    bool has_wait_polling;
>>>>    };
>>>>
>>>>    struct tegra_qspi_client_data {
>>>>        int tx_clk_tap_delay;
>>>>        int rx_clk_tap_delay;
>>>> +    bool wait_polling;
>>>>    };
>>>>
>>>>    struct tegra_qspi {
>>>> @@ -833,6 +836,11 @@ static u32 tegra_qspi_setup_transfer_one(struct 
>>>> spi_device *spi, struct spi_tran
>>>>            else
>>>>                command1 |= QSPI_CONTROL_MODE_0;
>>>>
>>>> +        if (tqspi->soc_data->cmb_xfer_capable)
>>>> +            command1 &= ~QSPI_CS_SW_HW;
>>>> +        else
>>>> +            command1 |= QSPI_CS_SW_HW;
>>>> +
>>>>            if (spi->mode & SPI_CS_HIGH)
>>>>                command1 |= QSPI_CS_SW_VAL;
>>>>            else
>>>> @@ -917,6 +925,7 @@ static int tegra_qspi_start_transfer_one(struct 
>>>> spi_device *spi,
>>>>
>>>>    static struct tegra_qspi_client_data 
>>>> *tegra_qspi_parse_cdata_dt(struct spi_device *spi)
>>>>    {
>>>> +    struct tegra_qspi *tqspi = spi_master_get_devdata(spi->master);
>>>>        struct tegra_qspi_client_data *cdata;
>>>>
>>>>        cdata = devm_kzalloc(&spi->dev, sizeof(*cdata), GFP_KERNEL);
>>>> @@ -927,6 +936,11 @@ static struct tegra_qspi_client_data 
>>>> *tegra_qspi_parse_cdata_dt(struct spi_devic
>>>>                     &cdata->tx_clk_tap_delay);
>>>>        device_property_read_u32(&spi->dev, "nvidia,rx-clk-tap-delay",
>>>>                     &cdata->rx_clk_tap_delay);
>>>> +    if (tqspi->soc_data->has_wait_polling)
>>>> +        cdata->wait_polling = device_property_read_bool
>>>> +                    (&spi->dev,
>>>> +                     "nvidia,wait-polling");
>>>> +
>>>
>>>
>>> This looks odd. Why do we need this device-tree property if it is
>>> already specified in the SoC data?
>> Soc data specifies chip is capable of wait-polling.
>> Wait polling still has to be selected on slave devices that can 
>> support it.
>> I will add one line description for the properties in next version.
> 
> 
> I can't say I am familiar with this, but it seems that the ideal 
> solution would be able to detect if this needs to be enabled depending 
> on the device connected. Is that not possible?

Also, given that Grace supports 4 chip-selects per device, how does this 
work if there is TPM connected to one chip-select and something else 
connected to another?

Jon

-- 
nvpublic