Received: by 2002:a05:6a10:413:0:0:0:0 with SMTP id 19csp1652556pxp; Thu, 17 Mar 2022 13:40:01 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyuE3I846TX3aSxSUeR6yEZsj1Cfac942+ZQYt9IImd8jOCEtBJcOUEOWDoD1hYmaUmPlJi X-Received: by 2002:a17:902:9a06:b0:153:4c5e:6a5b with SMTP id v6-20020a1709029a0600b001534c5e6a5bmr6569867plp.93.1647549601431; Thu, 17 Mar 2022 13:40:01 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1647549601; cv=none; d=google.com; s=arc-20160816; b=lXB14zUR96esTSAekAddnQFl6ZH158Uvi9QkFESFcugqMhfwugVoK54sn3d5FdyM82 ajuzcmlvyCVZbroPIuXi4ruLqEURSBqDO29LAQCnGJMXJTaqB4r9qELimPiRbDqVXSy/ womMBWFAEusGCjrwsXymx/ZkkXWoTOcHN1s4PbQ0mhm/JigqZEQENbFXGYaqjZb7AJ3L fR4ygQPCFvGy5Cjd40ogIAdjUWvVS0AYjSLIDnE8m7hZEZIF80/efSxSpOkm79KOTVE+ k6BT1/6F/Xb+YxBbhzlkPiRfC3NErc4rdVTPUkoVXrYSzYGHrdpALeSEHOdv1OkyQeYX TeSQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:in-reply-to:from :references:cc:to:content-language:subject:user-agent:mime-version :date:message-id; bh=CS2oL7kY+yQsvANBGDw9ld/o/1zXg7jcgvvkVsV43vA=; b=VArNiS3bptljqNHJDB/4OSgB7f2NXtS7AZi25NYnoxMs9/RJVsRBAN0LD7+c5+qDFQ 6oVjOdeuaZF7C8aljrCdwAwVq3cPrY4YmA8BpjB2XI1M4QImgp+KmeoMG5CehDQ05y8Z Ot8XS+TGNc/UILZdWt2eiSS2c/5IgBM/EbvGlT7rDlVZ7HbOht916rRLERvzDh7O3tFD KtLC2WdWkCfcyjYkXLPAVTOHLBNl+peHwVx2sOblv/0SD4gdSSm4t+hCEdAN+pdRzNvI hFwcZSXS2NC6lKPjro8vsKUq5mx24Xidk0P+FdtgES08WBpeqs8PppMhBD+hQDI/gmh6 fWSg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Return-Path: Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net. [2620:137:e000::1:18]) by mx.google.com with ESMTPS id d18-20020a634f12000000b003816043ee64si3074862pgb.89.2022.03.17.13.40.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 17 Mar 2022 13:40:01 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:18 as permitted sender) client-ip=2620:137:e000::1:18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 287881DEA9A; Thu, 17 Mar 2022 13:08:35 -0700 (PDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233940AbiCQQIK (ORCPT + 99 others); Thu, 17 Mar 2022 12:08:10 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44412 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236373AbiCQQID (ORCPT ); Thu, 17 Mar 2022 12:08:03 -0400 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 6A17D214075; Thu, 17 Mar 2022 09:06:46 -0700 (PDT) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 107241424; Thu, 17 Mar 2022 09:06:46 -0700 (PDT) Received: from [10.57.41.19] (unknown [10.57.41.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 6DCFF3F7B4; Thu, 17 Mar 2022 09:06:41 -0700 (PDT) Message-ID: Date: Thu, 17 Mar 2022 17:07:01 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.5.0 Subject: Re: [PATCH v1 2/3] cpufreq: CPPC: Add per_cpu efficiency_class Content-Language: en-US To: Marc Zyngier Cc: linux-kernel@vger.kernel.org, Ionela.Voinescu@arm.com, Lukasz.Luba@arm.com, Morten.Rasmussen@arm.com, Dietmar.Eggemann@arm.com, mka@chromium.org, daniel.lezcano@linaro.org, Catalin Marinas , Will Deacon , "Rafael J. Wysocki" , Viresh Kumar , Mark Rutland , Ard Biesheuvel , Fuad Tabba , Rob Herring , linux-arm-kernel@lists.infradead.org, linux-pm@vger.kernel.org References: <20220317133419.3901736-1-Pierre.Gondois@arm.com> <20220317133419.3901736-3-Pierre.Gondois@arm.com> From: Pierre Gondois In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,NICE_REPLY_A, RDNS_NONE,SPF_HELO_NONE,T_SCC_BODY_TEXT_LINE autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 3/17/22 16:13, Marc Zyngier wrote: > On 2022-03-17 13:34, Pierre Gondois wrote: >> In ACPI, describing power efficiency of CPUs can be done through the >> following arm specific field: >> ACPI 6.4, s5.2.12.14 'GIC CPU Interface (GICC) Structure', >> 'Processor Power Efficiency Class field': >> Describes the relative power efficiency of the associated pro- >> cessor. Lower efficiency class numbers are more efficient than >> higher ones (e.g. efficiency class 0 should be treated as more >> efficient than efficiency class 1). However, absolute values >> of this number have no meaning: 2 isn’t necessarily half as >> efficient as 1. >> >> The efficiency_class field is stored in the GicC structure of the >> ACPI MADT table and it's currently supported in Linux for arm64 only. >> Thus, this new functionality is introduced for arm64 only. >> >> To allow the cppc_cpufreq driver to know and preprocess the >> efficiency_class values of all the CPUs, add a per_cpu efficiency_class >> variable to store them. Also add a static efficiency_class_populated >> to let the driver know efficiency_class values are usable and register >> an artificial Energy Model (EM) based on normalized class values. >> >> At least 2 different efficiency classes must be present, >> otherwise there is no use in creating an Energy Model. >> >> The efficiency_class values are squeezed in [0:#efficiency_class-1] >> while conserving the order. For instance, efficiency classes of: >> [111, 212, 250] >> will be mapped to: >> [0 (was 111), 1 (was 212), 2 (was 250)]. >> >> Each policy being independently registered in the driver, populating >> the per_cpu efficiency_class is done only once at the driver >> initialization. This prevents from having each policy re-searching the >> efficiency_class values of other CPUs. >> >> The patch also exports acpi_cpu_get_madt_gicc() to fetch the GicC >> structure of the ACPI MADT table for each CPU. >> >> Signed-off-by: Pierre Gondois >> --- >> arch/arm64/kernel/smp.c | 1 + >> drivers/cpufreq/cppc_cpufreq.c | 55 ++++++++++++++++++++++++++++++++++ >> 2 files changed, 56 insertions(+) >> >> diff --git a/arch/arm64/kernel/smp.c b/arch/arm64/kernel/smp.c >> index 27df5c1e6baa..56637cbea5d6 100644 >> --- a/arch/arm64/kernel/smp.c >> +++ b/arch/arm64/kernel/smp.c >> @@ -512,6 +512,7 @@ struct acpi_madt_generic_interrupt >> *acpi_cpu_get_madt_gicc(int cpu) >> { >> return &cpu_madt_gicc[cpu]; >> } >> +EXPORT_SYMBOL(acpi_cpu_get_madt_gicc); > > Why not EXPORT_SYMBOL_GPL()? From what I understand, this could be made EXPORT_SYMBOL_GPL(). The only reason was that the other symbol exportation in the file wasn't restricted to GPL. > >> >> /* >> * acpi_map_gic_cpu_interface - parse processor MADT entry >> diff --git a/drivers/cpufreq/cppc_cpufreq.c >> b/drivers/cpufreq/cppc_cpufreq.c >> index 8f950fe72765..a6cd95c3b474 100644 >> --- a/drivers/cpufreq/cppc_cpufreq.c >> +++ b/drivers/cpufreq/cppc_cpufreq.c >> @@ -422,12 +422,66 @@ static unsigned int >> cppc_cpufreq_get_transition_delay_us(unsigned int cpu) >> return cppc_get_transition_latency(cpu) / NSEC_PER_USEC; >> } >> >> +static bool efficiency_class_populated; >> +static DEFINE_PER_CPU(unsigned int, efficiency_class); >> + >> +static int populate_efficiency_class(void) >> +{ >> + unsigned int min = UINT_MAX, max = 0, class; >> + struct acpi_madt_generic_interrupt *gicc; >> + int cpu; >> + >> + for_each_possible_cpu(cpu) { >> + gicc = acpi_cpu_get_madt_gicc(cpu); >> + if (!gicc) >> + return -ENODEV; > > How can that happen if you made it here using ACPI? This is effectively an extra check. This could be removed. > >> + >> + per_cpu(efficiency_class, cpu) = gicc->efficiency_class; >> + min = min_t(unsigned int, min, gicc->efficiency_class); >> + max = max_t(unsigned int, max, gicc->efficiency_class); >> + } > > Why don't you use a temporary bitmap of 256 bits, tracking > the classes that are actually being used? > >> + >> + if (min == max) { > > This would become (bitmap_weight(used_classes) <= 1). Then from > the same construct you know how many different classes you have. > You also have the min, max, and all the values in between. > >> + pr_debug("Efficiency classes are all equal (=%d). " >> + "No EM registered", max); >> + return -EINVAL; >> + } >> + >> + /* >> + * Squeeze efficiency class values on [0:#efficiency_class-1]. >> + * Values are per spec in [0:255]. >> + */ >> + for (class = 0; class < 256; class++) { >> + unsigned int new_min, curr; >> + >> + new_min = UINT_MAX; >> + for_each_possible_cpu(cpu) { >> + curr = per_cpu(efficiency_class, cpu); >> + if (curr == min) >> + per_cpu(efficiency_class, cpu) = class; >> + else if (curr > min) >> + new_min = min(new_min, curr); >> + } >> + >> + if (new_min == UINT_MAX) >> + break; >> + min = new_min; >> + } > > I find it really hard to reason about this because you are > dynamically rewriting the values you keep reevaluating. > > How about something like this, which I find more readable: > > DECLARE_BITMAP(used_classes, 256) = {}; > int class, index, cpu; > > for_each_possible_cpu(cpu) { > unsigned int ec; > > ec = acpi_cpu_get_madt_gicc(cpu)->efficiency_class & 0xff; > bitmap_set(ec, &used_classes); > } > > if (bitmap_weight(&used_classes, 256) <= 1) > return; > > index = 0; > > for_each_set_bit(class, &used_classes, 256) { > for_each_possible_cpu(cpu) { > if (acpi_cpu_get_madt_gicc(cpu)->efficiency_class == class) > per_cpu(efficiency_class, cpu) = index; > } > > index++; > } This is effectively much more readable. Thanks for the code snippet. Regards, Pierre > > > Thanks, > > M.