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[2620:137:e000::1:18]) by mx.google.com with ESMTPS id b22-20020a63d316000000b003816043ef49si3674157pgg.318.2022.03.17.13.59.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 17 Mar 2022 13:59:29 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:18 as permitted sender) client-ip=2620:137:e000::1:18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 42E4114D7A7; Thu, 17 Mar 2022 13:25:40 -0700 (PDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229665AbiCQU0i (ORCPT + 99 others); Thu, 17 Mar 2022 16:26:38 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34878 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229595AbiCQU0g (ORCPT ); Thu, 17 Mar 2022 16:26:36 -0400 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id D6DA114CD08; Thu, 17 Mar 2022 13:25:19 -0700 (PDT) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 941081FB; Thu, 17 Mar 2022 13:25:19 -0700 (PDT) Received: from [10.57.43.230] (unknown [10.57.43.230]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 7FC503F766; Thu, 17 Mar 2022 13:25:17 -0700 (PDT) Message-ID: <558f0c92-c499-daca-e1ad-2b16137f8c06@arm.com> Date: Thu, 17 Mar 2022 20:25:12 +0000 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; rv:91.0) Gecko/20100101 Thunderbird/91.7.0 Subject: Re: [PATCH v2 2/3] dt-bindings: timer: Document arm, cortex-a7-timer in arch timer Content-Language: en-GB To: Kuldeep Singh , Marc Zyngier , Daniel Lezcano , Thomas Gleixner , Rob Herring , Marc Zyngier , Mark Rutland Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org References: <20220317191527.96237-1-singh.kuldeep87k@gmail.com> <20220317191527.96237-3-singh.kuldeep87k@gmail.com> From: Robin Murphy In-Reply-To: <20220317191527.96237-3-singh.kuldeep87k@gmail.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,NICE_REPLY_A, RDNS_NONE,SPF_HELO_NONE,T_SCC_BODY_TEXT_LINE autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 2022-03-17 19:15, Kuldeep Singh wrote: > Renesas RZ/N1D platform uses compatible "arm,cortex-a7-timer" in > conjugation with "arm,armv7-timer". Since, initial entry is not > documented, it start raising dtbs_check warnings. > > ['arm,cortex-a7-timer', 'arm,armv7-timer'] is too long > 'arm,cortex-a7-timer' is not one of ['arm,armv7-timer', 'arm,armv8-timer'] > 'arm,cortex-a7-timer' is not one of ['arm,cortex-a15-timer'] > > Document this compatible to address it. The motivation to add this > change is taken from an already existing entry "arm,cortex-a15-timer". > Please note, this will not hurt any arch timer users. Eh, if it's never been documented or supported, I say just get rid of it. The arch timer interface is by definition part of a CPU, and we can tell what the CPU is by reading its ID registers. Indeed that's how the driver handles the non-zero number of CPU-specific errata that already exist - we don't need compatibles for that. In some ways it might have been nice to have *SoC-specific* compatibles given the difficulty some integrators seem to have had in wiring up a stable count *to* the interface, but it's not like they could be magically added to already-deployed DTs after a bug is discovered, and nor could we have mandated them from day 1 just in case and subsequently maintained a binding that is just an ever-growing list of every SoC. Oh well. Robin. > Signed-off-by: Kuldeep Singh > --- > Documentation/devicetree/bindings/timer/arm,arch_timer.yaml | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/Documentation/devicetree/bindings/timer/arm,arch_timer.yaml b/Documentation/devicetree/bindings/timer/arm,arch_timer.yaml > index ba2910f0a7b2..ea390e5df71d 100644 > --- a/Documentation/devicetree/bindings/timer/arm,arch_timer.yaml > +++ b/Documentation/devicetree/bindings/timer/arm,arch_timer.yaml > @@ -26,6 +26,7 @@ properties: > - arm,armv8-timer > - items: > - enum: > + - arm,cortex-a7-timer > - arm,cortex-a15-timer > - const: arm,armv7-timer >