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[209.85.208.181]) by smtp.gmail.com with ESMTPSA id b2-20020a196442000000b00443c5b81ce0sm581671lfj.180.2022.03.17.16.31.36 for (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 17 Mar 2022 16:31:36 -0700 (PDT) Received: by mail-lj1-f181.google.com with SMTP id s25so9284277lji.5 for ; Thu, 17 Mar 2022 16:31:36 -0700 (PDT) X-Received: by 2002:a2e:a78f:0:b0:249:21ce:6d53 with SMTP id c15-20020a2ea78f000000b0024921ce6d53mr4379261ljf.164.1647559895803; Thu, 17 Mar 2022 16:31:35 -0700 (PDT) MIME-Version: 1.0 References: <20220317231959.GN614@gate.crashing.org> In-Reply-To: <20220317231959.GN614@gate.crashing.org> From: Linus Torvalds Date: Thu, 17 Mar 2022 16:31:19 -0700 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH v5] x86: use builtins to read eflags To: Segher Boessenkool Cc: Bill Wendling , Nick Desaulniers , "H. Peter Anvin" , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , "maintainer:X86 ARCHITECTURE (32-BIT AND 64-BIT)" , Nathan Chancellor , Juergen Gross , Peter Zijlstra , Andy Lutomirski , llvm@lists.linux.dev, LKML , linux-toolchains Content-Type: text/plain; charset="UTF-8" X-Spam-Status: No, score=-1.8 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, Mar 17, 2022 at 4:25 PM Segher Boessenkool wrote: > > > I still think that from a sanity standpoint, it would be good to > > actually strengthen the semantics of "asm volatile" to literally act > > as - and be ordered with - volatile memory accesses. > > > > But I guess that's water under the bridge. > > That is what it has actually done since forever. See C 5.1.2.3. For > GCC, "asm volatile" has a side effect like in /2 there as well, as does > unspec_volatile (an internal GCC thing used to implement certain > builtins, among other things). Oh, so two "asm volatile" statements _are_ in fact defined to be ordered wrt each other? Because the gcc docs certainly don't say that ;( Yeah, yeah, dead code can be removed, whether volatile or not. That's true of "*(volatile int *)x" too. It's not the dead code that is the interesting case, though.. Is this also well-defined ordering-wise: asm volatile("do_something"); WRITE_ONCE(x, 1); (where "WRITE_ONCE()" is that kernel macro that just uses a volatile pointer assignment to force the access)? And could we get that documented? Linus