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[2620:137:e000::1:20]) by mx.google.com with ESMTP id l11-20020a056a00140b00b004f3a81da9a5si8796590pfu.234.2022.03.18.10.52.35; Fri, 18 Mar 2022 10:52:50 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=KVnfUtpP; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234229AbiCRJLg (ORCPT + 99 others); Fri, 18 Mar 2022 05:11:36 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60734 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229497AbiCRJLa (ORCPT ); Fri, 18 Mar 2022 05:11:30 -0400 Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 10E8217ECE6; Fri, 18 Mar 2022 02:10:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1647594612; x=1679130612; h=message-id:date:mime-version:subject:to:cc:references: from:in-reply-to:content-transfer-encoding; bh=BoEOAB/3Zl2br4U4pwEmdt2puKNHoRTEMJxj497TT0s=; b=KVnfUtpPzRUAqdz8lRfcCZ2zW0lFL4VQRPBZ1RZ+zfyAkxNtsWnY3Wil LlvXVbGj6Kt/ae1hQJ6pJBXePwSguQvzsz9agn7venfKNXsFywpmWEubc 5O6DdQvss1n//k79a+TkSIWlDtnLD4OOblBSwLTxjXFBb0MwbdxFSuEXZ OXtl443snhlRZHw156o29taWvpBtBc7tZU/IP5PVyNELDCIZdaotAqCcU yL4HCHcGUzt5KMbAxQ8aX23HR4bUosubVHWfhB4lv8xExlCCaMRRTNrfC XPtT9Zy7BEKDxKvLH1kH/bYPqJGUeOUCFY8kMogjEVgaMWtkRIoOznpGM w==; X-IronPort-AV: E=McAfee;i="6200,9189,10289"; a="254653644" X-IronPort-AV: E=Sophos;i="5.90,191,1643702400"; d="scan'208";a="254653644" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Mar 2022 02:09:49 -0700 X-IronPort-AV: E=Sophos;i="5.90,191,1643702400"; d="scan'208";a="558336166" Received: from xingzhen-mobl.ccr.corp.intel.com (HELO [10.255.31.171]) ([10.255.31.171]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Mar 2022 02:09:43 -0700 Message-ID: <99cb68b7-ba93-651b-cbec-3a11e2d4f817@linux.intel.com> Date: Fri, 18 Mar 2022 17:09:40 +0800 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:91.0) Gecko/20100101 Thunderbird/91.7.0 Subject: Re: [PATCH 1/8] perf vendor events: Update events for CascadelakeX Content-Language: en-US To: Ian Rogers , Kan Liang , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Maxime Coquelin , Alexandre Torgue , Andi Kleen , James Clark , John Garry , linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org Cc: Stephane Eranian References: <20220317182858.484474-1-irogers@google.com> From: Xing Zhengjun In-Reply-To: <20220317182858.484474-1-irogers@google.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 3/18/2022 2:28 AM, Ian Rogers wrote: > The change: > https://github.com/intel/event-converter-for-linux-perf/commit/fc680410402e394eed6a1ebd909c9f649d3ed3ef > moved certain "other" type of events in to the cache topic. Update the > perf json files for this change. > > Tested: > ``` > ... > 6: Parse event definition strings : Ok > 7: Simple expression parser : Ok > 8: PERF_RECORD_* events & perf_sample fields : Ok > 9: Parse perf pmu format : Ok > 10: PMU events : > 10.1: PMU event table sanity : Ok > 10.2: PMU event map aliases : Ok > 10.3: Parsing of PMU event table metrics : Ok > 10.4: Parsing of PMU event table metrics with fake PMUs : Ok > ... > 68: Parse and process metrics : Ok > ... > 89: perf all metricgroups test : Ok > 90: perf all metrics test : FAILED! > 91: perf all PMU test : Ok > ... > ``` > > Test 90 failed due to MEM_PMM_Read_Latency as the test machine > lacks optane memory, and the divide by 0 causes the metric not to > print - which is intended behavior. > > Signed-off-by: Ian Rogers Reviewed-by: Zhengjun Xing > --- > .../arch/x86/cascadelakex/cache.json | 6588 +++++++++++++++ > .../arch/x86/cascadelakex/other.json | 7446 +---------------- > 2 files changed, 7017 insertions(+), 7017 deletions(-) > > diff --git a/tools/perf/pmu-events/arch/x86/cascadelakex/cache.json b/tools/perf/pmu-events/arch/x86/cascadelakex/cache.json > index 732bf51e35af..aa906a7fa520 100644 > --- a/tools/perf/pmu-events/arch/x86/cascadelakex/cache.json > +++ b/tools/perf/pmu-events/arch/x86/cascadelakex/cache.json > @@ -602,6 +602,6558 @@ > "SampleAfterValue": "100003", > "UMask": "0x80" > }, > + { > + "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT.ANY_SNOOP OCR.ALL_DATA_RD.L3_HIT.ANY_SNOOP OCR.ALL_DATA_RD.L3_HIT.ANY_SNOOP", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_DATA_RD.L3_HIT.ANY_SNOOP", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x3F803C0491", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT.HITM_OTHER_CORE OCR.ALL_DATA_RD.L3_HIT.HITM_OTHER_CORE OCR.ALL_DATA_RD.L3_HIT.HITM_OTHER_CORE", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_DATA_RD.L3_HIT.HITM_OTHER_CORE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x10003C0491", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD OCR.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD OCR.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x8003C0491", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x4003C0491", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT.NO_SNOOP_NEEDED OCR.ALL_DATA_RD.L3_HIT.NO_SNOOP_NEEDED OCR.ALL_DATA_RD.L3_HIT.NO_SNOOP_NEEDED", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_DATA_RD.L3_HIT.NO_SNOOP_NEEDED", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x1003C0491", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x8007C0491", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT.SNOOP_MISS OCR.ALL_DATA_RD.L3_HIT.SNOOP_MISS", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_DATA_RD.L3_HIT.SNOOP_MISS", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x2003C0491", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT.SNOOP_NONE OCR.ALL_DATA_RD.L3_HIT.SNOOP_NONE", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_DATA_RD.L3_HIT.SNOOP_NONE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x803C0491", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_E.ANY_SNOOP OCR.ALL_DATA_RD.L3_HIT_E.ANY_SNOOP", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_DATA_RD.L3_HIT_E.ANY_SNOOP", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x3F80080491", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_E.HITM_OTHER_CORE OCR.ALL_DATA_RD.L3_HIT_E.HITM_OTHER_CORE", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_DATA_RD.L3_HIT_E.HITM_OTHER_CORE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x1000080491", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD OCR.ALL_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x800080491", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD OCR.ALL_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x400080491", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED OCR.ALL_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x100080491", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_E.SNOOP_MISS", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_DATA_RD.L3_HIT_E.SNOOP_MISS", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x200080491", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_E.SNOOP_NONE", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_DATA_RD.L3_HIT_E.SNOOP_NONE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x80080491", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_F.ANY_SNOOP OCR.ALL_DATA_RD.L3_HIT_F.ANY_SNOOP", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_DATA_RD.L3_HIT_F.ANY_SNOOP", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x3F80200491", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_F.HITM_OTHER_CORE OCR.ALL_DATA_RD.L3_HIT_F.HITM_OTHER_CORE", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_DATA_RD.L3_HIT_F.HITM_OTHER_CORE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x1000200491", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD OCR.ALL_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x800200491", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD OCR.ALL_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x400200491", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED OCR.ALL_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x100200491", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_F.SNOOP_MISS", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_DATA_RD.L3_HIT_F.SNOOP_MISS", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x200200491", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_F.SNOOP_NONE", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_DATA_RD.L3_HIT_F.SNOOP_NONE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x80200491", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_M.ANY_SNOOP OCR.ALL_DATA_RD.L3_HIT_M.ANY_SNOOP", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_DATA_RD.L3_HIT_M.ANY_SNOOP", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x3F80040491", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_M.HITM_OTHER_CORE OCR.ALL_DATA_RD.L3_HIT_M.HITM_OTHER_CORE", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_DATA_RD.L3_HIT_M.HITM_OTHER_CORE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x1000040491", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD OCR.ALL_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x800040491", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD OCR.ALL_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x400040491", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED OCR.ALL_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x100040491", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_M.SNOOP_MISS", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_DATA_RD.L3_HIT_M.SNOOP_MISS", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x200040491", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_M.SNOOP_NONE", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_DATA_RD.L3_HIT_M.SNOOP_NONE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x80040491", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_S.ANY_SNOOP OCR.ALL_DATA_RD.L3_HIT_S.ANY_SNOOP", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_DATA_RD.L3_HIT_S.ANY_SNOOP", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x3F80100491", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_S.HITM_OTHER_CORE OCR.ALL_DATA_RD.L3_HIT_S.HITM_OTHER_CORE", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_DATA_RD.L3_HIT_S.HITM_OTHER_CORE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x1000100491", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD OCR.ALL_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x800100491", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD OCR.ALL_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x400100491", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED OCR.ALL_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x100100491", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_S.SNOOP_MISS", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_DATA_RD.L3_HIT_S.SNOOP_MISS", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x200100491", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_S.SNOOP_NONE", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_DATA_RD.L3_HIT_S.SNOOP_NONE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x80100491", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT.ANY_SNOOP OCR.ALL_PF_DATA_RD.L3_HIT.ANY_SNOOP OCR.ALL_PF_DATA_RD.L3_HIT.ANY_SNOOP", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT.ANY_SNOOP", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x3F803C0490", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT.HITM_OTHER_CORE OCR.ALL_PF_DATA_RD.L3_HIT.HITM_OTHER_CORE OCR.ALL_PF_DATA_RD.L3_HIT.HITM_OTHER_CORE", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT.HITM_OTHER_CORE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x10003C0490", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD OCR.ALL_PF_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD OCR.ALL_PF_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x8003C0490", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x4003C0490", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT.NO_SNOOP_NEEDED OCR.ALL_PF_DATA_RD.L3_HIT.NO_SNOOP_NEEDED OCR.ALL_PF_DATA_RD.L3_HIT.NO_SNOOP_NEEDED", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT.NO_SNOOP_NEEDED", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x1003C0490", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x8007C0490", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT.SNOOP_MISS OCR.ALL_PF_DATA_RD.L3_HIT.SNOOP_MISS", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT.SNOOP_MISS", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x2003C0490", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT.SNOOP_NONE OCR.ALL_PF_DATA_RD.L3_HIT.SNOOP_NONE", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT.SNOOP_NONE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x803C0490", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_E.ANY_SNOOP OCR.ALL_PF_DATA_RD.L3_HIT_E.ANY_SNOOP", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_E.ANY_SNOOP", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x3F80080490", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_E.HITM_OTHER_CORE OCR.ALL_PF_DATA_RD.L3_HIT_E.HITM_OTHER_CORE", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_E.HITM_OTHER_CORE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x1000080490", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD OCR.ALL_PF_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x800080490", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x400080490", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED OCR.ALL_PF_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x100080490", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_E.SNOOP_MISS", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_E.SNOOP_MISS", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x200080490", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_E.SNOOP_NONE", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_E.SNOOP_NONE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x80080490", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_F.ANY_SNOOP OCR.ALL_PF_DATA_RD.L3_HIT_F.ANY_SNOOP", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_F.ANY_SNOOP", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x3F80200490", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_F.HITM_OTHER_CORE OCR.ALL_PF_DATA_RD.L3_HIT_F.HITM_OTHER_CORE", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_F.HITM_OTHER_CORE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x1000200490", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD OCR.ALL_PF_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x800200490", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x400200490", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED OCR.ALL_PF_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x100200490", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_F.SNOOP_MISS", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_F.SNOOP_MISS", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x200200490", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_F.SNOOP_NONE", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_F.SNOOP_NONE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x80200490", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_M.ANY_SNOOP OCR.ALL_PF_DATA_RD.L3_HIT_M.ANY_SNOOP", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_M.ANY_SNOOP", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x3F80040490", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_M.HITM_OTHER_CORE OCR.ALL_PF_DATA_RD.L3_HIT_M.HITM_OTHER_CORE", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_M.HITM_OTHER_CORE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x1000040490", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD OCR.ALL_PF_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x800040490", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x400040490", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED OCR.ALL_PF_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x100040490", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_M.SNOOP_MISS", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_M.SNOOP_MISS", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x200040490", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_M.SNOOP_NONE", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_M.SNOOP_NONE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x80040490", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_S.ANY_SNOOP OCR.ALL_PF_DATA_RD.L3_HIT_S.ANY_SNOOP", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_S.ANY_SNOOP", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x3F80100490", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_S.HITM_OTHER_CORE OCR.ALL_PF_DATA_RD.L3_HIT_S.HITM_OTHER_CORE", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_S.HITM_OTHER_CORE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x1000100490", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD OCR.ALL_PF_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x800100490", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x400100490", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED OCR.ALL_PF_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x100100490", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_S.SNOOP_MISS", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_S.SNOOP_MISS", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x200100490", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_S.SNOOP_NONE", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_S.SNOOP_NONE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x80100490", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT.ANY_SNOOP OCR.ALL_PF_RFO.L3_HIT.ANY_SNOOP OCR.ALL_PF_RFO.L3_HIT.ANY_SNOOP", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_PF_RFO.L3_HIT.ANY_SNOOP", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x3F803C0120", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT.HITM_OTHER_CORE OCR.ALL_PF_RFO.L3_HIT.HITM_OTHER_CORE OCR.ALL_PF_RFO.L3_HIT.HITM_OTHER_CORE", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_PF_RFO.L3_HIT.HITM_OTHER_CORE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x10003C0120", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT.HIT_OTHER_CORE_FWD OCR.ALL_PF_RFO.L3_HIT.HIT_OTHER_CORE_FWD OCR.ALL_PF_RFO.L3_HIT.HIT_OTHER_CORE_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_PF_RFO.L3_HIT.HIT_OTHER_CORE_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x8003C0120", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_PF_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x4003C0120", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT.NO_SNOOP_NEEDED OCR.ALL_PF_RFO.L3_HIT.NO_SNOOP_NEEDED OCR.ALL_PF_RFO.L3_HIT.NO_SNOOP_NEEDED", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_PF_RFO.L3_HIT.NO_SNOOP_NEEDED", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x1003C0120", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT.SNOOP_HIT_WITH_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_PF_RFO.L3_HIT.SNOOP_HIT_WITH_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x8007C0120", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT.SNOOP_MISS OCR.ALL_PF_RFO.L3_HIT.SNOOP_MISS", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_PF_RFO.L3_HIT.SNOOP_MISS", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x2003C0120", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT.SNOOP_NONE OCR.ALL_PF_RFO.L3_HIT.SNOOP_NONE", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_PF_RFO.L3_HIT.SNOOP_NONE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x803C0120", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_E.ANY_SNOOP OCR.ALL_PF_RFO.L3_HIT_E.ANY_SNOOP", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_PF_RFO.L3_HIT_E.ANY_SNOOP", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x3F80080120", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_E.HITM_OTHER_CORE OCR.ALL_PF_RFO.L3_HIT_E.HITM_OTHER_CORE", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_PF_RFO.L3_HIT_E.HITM_OTHER_CORE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x1000080120", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD OCR.ALL_PF_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_PF_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x800080120", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_PF_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x400080120", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_E.NO_SNOOP_NEEDED OCR.ALL_PF_RFO.L3_HIT_E.NO_SNOOP_NEEDED", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_PF_RFO.L3_HIT_E.NO_SNOOP_NEEDED", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x100080120", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_E.SNOOP_MISS", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_PF_RFO.L3_HIT_E.SNOOP_MISS", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x200080120", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_E.SNOOP_NONE", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_PF_RFO.L3_HIT_E.SNOOP_NONE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x80080120", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_F.ANY_SNOOP OCR.ALL_PF_RFO.L3_HIT_F.ANY_SNOOP", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_PF_RFO.L3_HIT_F.ANY_SNOOP", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x3F80200120", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_F.HITM_OTHER_CORE OCR.ALL_PF_RFO.L3_HIT_F.HITM_OTHER_CORE", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_PF_RFO.L3_HIT_F.HITM_OTHER_CORE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x1000200120", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD OCR.ALL_PF_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_PF_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x800200120", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_PF_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x400200120", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_F.NO_SNOOP_NEEDED OCR.ALL_PF_RFO.L3_HIT_F.NO_SNOOP_NEEDED", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_PF_RFO.L3_HIT_F.NO_SNOOP_NEEDED", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x100200120", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_F.SNOOP_MISS", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_PF_RFO.L3_HIT_F.SNOOP_MISS", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x200200120", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_F.SNOOP_NONE", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_PF_RFO.L3_HIT_F.SNOOP_NONE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x80200120", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_M.ANY_SNOOP OCR.ALL_PF_RFO.L3_HIT_M.ANY_SNOOP", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_PF_RFO.L3_HIT_M.ANY_SNOOP", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x3F80040120", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_M.HITM_OTHER_CORE OCR.ALL_PF_RFO.L3_HIT_M.HITM_OTHER_CORE", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_PF_RFO.L3_HIT_M.HITM_OTHER_CORE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x1000040120", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD OCR.ALL_PF_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_PF_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x800040120", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_PF_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x400040120", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_M.NO_SNOOP_NEEDED OCR.ALL_PF_RFO.L3_HIT_M.NO_SNOOP_NEEDED", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_PF_RFO.L3_HIT_M.NO_SNOOP_NEEDED", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x100040120", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_M.SNOOP_MISS", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_PF_RFO.L3_HIT_M.SNOOP_MISS", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x200040120", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_M.SNOOP_NONE", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_PF_RFO.L3_HIT_M.SNOOP_NONE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x80040120", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_S.ANY_SNOOP OCR.ALL_PF_RFO.L3_HIT_S.ANY_SNOOP", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_PF_RFO.L3_HIT_S.ANY_SNOOP", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x3F80100120", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_S.HITM_OTHER_CORE OCR.ALL_PF_RFO.L3_HIT_S.HITM_OTHER_CORE", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_PF_RFO.L3_HIT_S.HITM_OTHER_CORE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x1000100120", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD OCR.ALL_PF_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_PF_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x800100120", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_PF_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x400100120", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_S.NO_SNOOP_NEEDED OCR.ALL_PF_RFO.L3_HIT_S.NO_SNOOP_NEEDED", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_PF_RFO.L3_HIT_S.NO_SNOOP_NEEDED", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x100100120", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_S.SNOOP_MISS", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_PF_RFO.L3_HIT_S.SNOOP_MISS", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x200100120", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_S.SNOOP_NONE", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_PF_RFO.L3_HIT_S.SNOOP_NONE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x80100120", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_READS.L3_HIT.ANY_SNOOP OCR.ALL_READS.L3_HIT.ANY_SNOOP OCR.ALL_READS.L3_HIT.ANY_SNOOP", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_READS.L3_HIT.ANY_SNOOP", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x3F803C07F7", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_READS.L3_HIT.HITM_OTHER_CORE OCR.ALL_READS.L3_HIT.HITM_OTHER_CORE OCR.ALL_READS.L3_HIT.HITM_OTHER_CORE", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_READS.L3_HIT.HITM_OTHER_CORE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x10003C07F7", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_READS.L3_HIT.HIT_OTHER_CORE_FWD OCR.ALL_READS.L3_HIT.HIT_OTHER_CORE_FWD OCR.ALL_READS.L3_HIT.HIT_OTHER_CORE_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_READS.L3_HIT.HIT_OTHER_CORE_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x8003C07F7", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_READS.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.ALL_READS.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.ALL_READS.L3_HIT.HIT_OTHER_CORE_NO_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_READS.L3_HIT.HIT_OTHER_CORE_NO_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x4003C07F7", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_READS.L3_HIT.NO_SNOOP_NEEDED OCR.ALL_READS.L3_HIT.NO_SNOOP_NEEDED OCR.ALL_READS.L3_HIT.NO_SNOOP_NEEDED", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_READS.L3_HIT.NO_SNOOP_NEEDED", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x1003C07F7", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_READS.L3_HIT.SNOOP_HIT_WITH_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_READS.L3_HIT.SNOOP_HIT_WITH_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x8007C07F7", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_READS.L3_HIT.SNOOP_MISS OCR.ALL_READS.L3_HIT.SNOOP_MISS", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_READS.L3_HIT.SNOOP_MISS", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x2003C07F7", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_READS.L3_HIT.SNOOP_NONE OCR.ALL_READS.L3_HIT.SNOOP_NONE", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_READS.L3_HIT.SNOOP_NONE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x803C07F7", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_READS.L3_HIT_E.ANY_SNOOP OCR.ALL_READS.L3_HIT_E.ANY_SNOOP", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_READS.L3_HIT_E.ANY_SNOOP", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x3F800807F7", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_READS.L3_HIT_E.HITM_OTHER_CORE OCR.ALL_READS.L3_HIT_E.HITM_OTHER_CORE", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_READS.L3_HIT_E.HITM_OTHER_CORE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x10000807F7", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_READS.L3_HIT_E.HIT_OTHER_CORE_FWD OCR.ALL_READS.L3_HIT_E.HIT_OTHER_CORE_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_READS.L3_HIT_E.HIT_OTHER_CORE_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x8000807F7", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_READS.L3_HIT_E.HIT_OTHER_CORE_NO_FWD OCR.ALL_READS.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_READS.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x4000807F7", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_READS.L3_HIT_E.NO_SNOOP_NEEDED OCR.ALL_READS.L3_HIT_E.NO_SNOOP_NEEDED", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_READS.L3_HIT_E.NO_SNOOP_NEEDED", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x1000807F7", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_READS.L3_HIT_E.SNOOP_MISS", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_READS.L3_HIT_E.SNOOP_MISS", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x2000807F7", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_READS.L3_HIT_E.SNOOP_NONE", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_READS.L3_HIT_E.SNOOP_NONE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x800807F7", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_READS.L3_HIT_F.ANY_SNOOP OCR.ALL_READS.L3_HIT_F.ANY_SNOOP", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_READS.L3_HIT_F.ANY_SNOOP", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x3F802007F7", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_READS.L3_HIT_F.HITM_OTHER_CORE OCR.ALL_READS.L3_HIT_F.HITM_OTHER_CORE", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_READS.L3_HIT_F.HITM_OTHER_CORE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x10002007F7", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_READS.L3_HIT_F.HIT_OTHER_CORE_FWD OCR.ALL_READS.L3_HIT_F.HIT_OTHER_CORE_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_READS.L3_HIT_F.HIT_OTHER_CORE_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x8002007F7", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_READS.L3_HIT_F.HIT_OTHER_CORE_NO_FWD OCR.ALL_READS.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_READS.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x4002007F7", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_READS.L3_HIT_F.NO_SNOOP_NEEDED OCR.ALL_READS.L3_HIT_F.NO_SNOOP_NEEDED", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_READS.L3_HIT_F.NO_SNOOP_NEEDED", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x1002007F7", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_READS.L3_HIT_F.SNOOP_MISS", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_READS.L3_HIT_F.SNOOP_MISS", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x2002007F7", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_READS.L3_HIT_F.SNOOP_NONE", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_READS.L3_HIT_F.SNOOP_NONE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x802007F7", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_READS.L3_HIT_M.ANY_SNOOP OCR.ALL_READS.L3_HIT_M.ANY_SNOOP", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_READS.L3_HIT_M.ANY_SNOOP", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x3F800407F7", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_READS.L3_HIT_M.HITM_OTHER_CORE OCR.ALL_READS.L3_HIT_M.HITM_OTHER_CORE", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_READS.L3_HIT_M.HITM_OTHER_CORE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x10000407F7", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_READS.L3_HIT_M.HIT_OTHER_CORE_FWD OCR.ALL_READS.L3_HIT_M.HIT_OTHER_CORE_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_READS.L3_HIT_M.HIT_OTHER_CORE_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x8000407F7", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_READS.L3_HIT_M.HIT_OTHER_CORE_NO_FWD OCR.ALL_READS.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_READS.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x4000407F7", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_READS.L3_HIT_M.NO_SNOOP_NEEDED OCR.ALL_READS.L3_HIT_M.NO_SNOOP_NEEDED", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_READS.L3_HIT_M.NO_SNOOP_NEEDED", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x1000407F7", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_READS.L3_HIT_M.SNOOP_MISS", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_READS.L3_HIT_M.SNOOP_MISS", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x2000407F7", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_READS.L3_HIT_M.SNOOP_NONE", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_READS.L3_HIT_M.SNOOP_NONE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x800407F7", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_READS.L3_HIT_S.ANY_SNOOP OCR.ALL_READS.L3_HIT_S.ANY_SNOOP", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_READS.L3_HIT_S.ANY_SNOOP", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x3F801007F7", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_READS.L3_HIT_S.HITM_OTHER_CORE OCR.ALL_READS.L3_HIT_S.HITM_OTHER_CORE", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_READS.L3_HIT_S.HITM_OTHER_CORE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x10001007F7", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_READS.L3_HIT_S.HIT_OTHER_CORE_FWD OCR.ALL_READS.L3_HIT_S.HIT_OTHER_CORE_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_READS.L3_HIT_S.HIT_OTHER_CORE_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x8001007F7", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_READS.L3_HIT_S.HIT_OTHER_CORE_NO_FWD OCR.ALL_READS.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_READS.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x4001007F7", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_READS.L3_HIT_S.NO_SNOOP_NEEDED OCR.ALL_READS.L3_HIT_S.NO_SNOOP_NEEDED", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_READS.L3_HIT_S.NO_SNOOP_NEEDED", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x1001007F7", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_READS.L3_HIT_S.SNOOP_MISS", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_READS.L3_HIT_S.SNOOP_MISS", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x2001007F7", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_READS.L3_HIT_S.SNOOP_NONE", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_READS.L3_HIT_S.SNOOP_NONE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x801007F7", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_RFO.L3_HIT.ANY_SNOOP OCR.ALL_RFO.L3_HIT.ANY_SNOOP OCR.ALL_RFO.L3_HIT.ANY_SNOOP", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_RFO.L3_HIT.ANY_SNOOP", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x3F803C0122", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_RFO.L3_HIT.HITM_OTHER_CORE OCR.ALL_RFO.L3_HIT.HITM_OTHER_CORE OCR.ALL_RFO.L3_HIT.HITM_OTHER_CORE", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_RFO.L3_HIT.HITM_OTHER_CORE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x10003C0122", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_RFO.L3_HIT.HIT_OTHER_CORE_FWD OCR.ALL_RFO.L3_HIT.HIT_OTHER_CORE_FWD OCR.ALL_RFO.L3_HIT.HIT_OTHER_CORE_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_RFO.L3_HIT.HIT_OTHER_CORE_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x8003C0122", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.ALL_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.ALL_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x4003C0122", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_RFO.L3_HIT.NO_SNOOP_NEEDED OCR.ALL_RFO.L3_HIT.NO_SNOOP_NEEDED OCR.ALL_RFO.L3_HIT.NO_SNOOP_NEEDED", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_RFO.L3_HIT.NO_SNOOP_NEEDED", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x1003C0122", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_RFO.L3_HIT.SNOOP_HIT_WITH_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_RFO.L3_HIT.SNOOP_HIT_WITH_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x8007C0122", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_RFO.L3_HIT.SNOOP_MISS OCR.ALL_RFO.L3_HIT.SNOOP_MISS", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_RFO.L3_HIT.SNOOP_MISS", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x2003C0122", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_RFO.L3_HIT.SNOOP_NONE OCR.ALL_RFO.L3_HIT.SNOOP_NONE", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_RFO.L3_HIT.SNOOP_NONE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x803C0122", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_RFO.L3_HIT_E.ANY_SNOOP OCR.ALL_RFO.L3_HIT_E.ANY_SNOOP", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_RFO.L3_HIT_E.ANY_SNOOP", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x3F80080122", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_RFO.L3_HIT_E.HITM_OTHER_CORE OCR.ALL_RFO.L3_HIT_E.HITM_OTHER_CORE", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_RFO.L3_HIT_E.HITM_OTHER_CORE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x1000080122", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD OCR.ALL_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x800080122", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD OCR.ALL_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x400080122", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_RFO.L3_HIT_E.NO_SNOOP_NEEDED OCR.ALL_RFO.L3_HIT_E.NO_SNOOP_NEEDED", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_RFO.L3_HIT_E.NO_SNOOP_NEEDED", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x100080122", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_RFO.L3_HIT_E.SNOOP_MISS", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_RFO.L3_HIT_E.SNOOP_MISS", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x200080122", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_RFO.L3_HIT_E.SNOOP_NONE", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_RFO.L3_HIT_E.SNOOP_NONE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x80080122", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_RFO.L3_HIT_F.ANY_SNOOP OCR.ALL_RFO.L3_HIT_F.ANY_SNOOP", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_RFO.L3_HIT_F.ANY_SNOOP", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x3F80200122", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_RFO.L3_HIT_F.HITM_OTHER_CORE OCR.ALL_RFO.L3_HIT_F.HITM_OTHER_CORE", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_RFO.L3_HIT_F.HITM_OTHER_CORE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x1000200122", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD OCR.ALL_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x800200122", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD OCR.ALL_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x400200122", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_RFO.L3_HIT_F.NO_SNOOP_NEEDED OCR.ALL_RFO.L3_HIT_F.NO_SNOOP_NEEDED", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_RFO.L3_HIT_F.NO_SNOOP_NEEDED", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x100200122", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_RFO.L3_HIT_F.SNOOP_MISS", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_RFO.L3_HIT_F.SNOOP_MISS", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x200200122", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_RFO.L3_HIT_F.SNOOP_NONE", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_RFO.L3_HIT_F.SNOOP_NONE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x80200122", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_RFO.L3_HIT_M.ANY_SNOOP OCR.ALL_RFO.L3_HIT_M.ANY_SNOOP", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_RFO.L3_HIT_M.ANY_SNOOP", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x3F80040122", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_RFO.L3_HIT_M.HITM_OTHER_CORE OCR.ALL_RFO.L3_HIT_M.HITM_OTHER_CORE", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_RFO.L3_HIT_M.HITM_OTHER_CORE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x1000040122", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD OCR.ALL_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x800040122", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD OCR.ALL_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x400040122", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_RFO.L3_HIT_M.NO_SNOOP_NEEDED OCR.ALL_RFO.L3_HIT_M.NO_SNOOP_NEEDED", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_RFO.L3_HIT_M.NO_SNOOP_NEEDED", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x100040122", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_RFO.L3_HIT_M.SNOOP_MISS", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_RFO.L3_HIT_M.SNOOP_MISS", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x200040122", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_RFO.L3_HIT_M.SNOOP_NONE", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_RFO.L3_HIT_M.SNOOP_NONE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x80040122", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_RFO.L3_HIT_S.ANY_SNOOP OCR.ALL_RFO.L3_HIT_S.ANY_SNOOP", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_RFO.L3_HIT_S.ANY_SNOOP", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x3F80100122", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_RFO.L3_HIT_S.HITM_OTHER_CORE OCR.ALL_RFO.L3_HIT_S.HITM_OTHER_CORE", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_RFO.L3_HIT_S.HITM_OTHER_CORE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x1000100122", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD OCR.ALL_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x800100122", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD OCR.ALL_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x400100122", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_RFO.L3_HIT_S.NO_SNOOP_NEEDED OCR.ALL_RFO.L3_HIT_S.NO_SNOOP_NEEDED", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_RFO.L3_HIT_S.NO_SNOOP_NEEDED", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x100100122", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_RFO.L3_HIT_S.SNOOP_MISS", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_RFO.L3_HIT_S.SNOOP_MISS", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x200100122", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_RFO.L3_HIT_S.SNOOP_NONE", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_RFO.L3_HIT_S.SNOOP_NONE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x80100122", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT.ANY_SNOOP OCR.DEMAND_CODE_RD.L3_HIT.ANY_SNOOP", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.ANY_SNOOP", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x3F803C0004", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT.HITM_OTHER_CORE OCR.DEMAND_CODE_RD.L3_HIT.HITM_OTHER_CORE", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.HITM_OTHER_CORE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x10003C0004", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT.HIT_OTHER_CORE_FWD OCR.DEMAND_CODE_RD.L3_HIT.HIT_OTHER_CORE_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.HIT_OTHER_CORE_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x8003C0004", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.DEMAND_CODE_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x4003C0004", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT.NO_SNOOP_NEEDED OCR.DEMAND_CODE_RD.L3_HIT.NO_SNOOP_NEEDED", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.NO_SNOOP_NEEDED", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x1003C0004", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all demand code reads", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_HIT_WITH_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x8007C0004", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_MISS", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_MISS", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x2003C0004", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_NONE", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_NONE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x803C0004", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_E.ANY_SNOOP", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_E.ANY_SNOOP", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x3F80080004", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_E.HITM_OTHER_CORE", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_E.HITM_OTHER_CORE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x1000080004", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_E.HIT_OTHER_CORE_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_E.HIT_OTHER_CORE_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x800080004", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x400080004", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_E.NO_SNOOP_NEEDED", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_E.NO_SNOOP_NEEDED", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x100080004", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all demand code reads", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_E.SNOOP_MISS", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x200080004", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all demand code reads", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_E.SNOOP_NONE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x80080004", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_F.ANY_SNOOP", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_F.ANY_SNOOP", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x3F80200004", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_F.HITM_OTHER_CORE", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_F.HITM_OTHER_CORE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x1000200004", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_F.HIT_OTHER_CORE_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_F.HIT_OTHER_CORE_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x800200004", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x400200004", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_F.NO_SNOOP_NEEDED", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_F.NO_SNOOP_NEEDED", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x100200004", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all demand code reads", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_F.SNOOP_MISS", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x200200004", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all demand code reads", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_F.SNOOP_NONE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x80200004", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_M.ANY_SNOOP", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_M.ANY_SNOOP", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x3F80040004", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_M.HITM_OTHER_CORE", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_M.HITM_OTHER_CORE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x1000040004", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_M.HIT_OTHER_CORE_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_M.HIT_OTHER_CORE_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x800040004", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x400040004", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_M.NO_SNOOP_NEEDED", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_M.NO_SNOOP_NEEDED", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x100040004", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all demand code reads", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_M.SNOOP_MISS", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x200040004", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all demand code reads", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_M.SNOOP_NONE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x80040004", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_S.ANY_SNOOP", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_S.ANY_SNOOP", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x3F80100004", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_S.HITM_OTHER_CORE", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_S.HITM_OTHER_CORE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x1000100004", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_S.HIT_OTHER_CORE_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_S.HIT_OTHER_CORE_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x800100004", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x400100004", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_S.NO_SNOOP_NEEDED", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_S.NO_SNOOP_NEEDED", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x100100004", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all demand code reads", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_S.SNOOP_MISS", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x200100004", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all demand code reads", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_S.SNOOP_NONE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x80100004", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT.ANY_SNOOP OCR.DEMAND_DATA_RD.L3_HIT.ANY_SNOOP", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.ANY_SNOOP", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x3F803C0001", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE OCR.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x10003C0001", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD OCR.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x8003C0001", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x4003C0001", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT.NO_SNOOP_NEEDED OCR.DEMAND_DATA_RD.L3_HIT.NO_SNOOP_NEEDED", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.NO_SNOOP_NEEDED", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x1003C0001", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts demand data reads", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x8007C0001", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_MISS", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_MISS", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x2003C0001", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_NONE", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_NONE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x803C0001", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_E.ANY_SNOOP", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_E.ANY_SNOOP", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x3F80080001", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_E.HITM_OTHER_CORE", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_E.HITM_OTHER_CORE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x1000080001", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x800080001", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x400080001", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x100080001", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts demand data reads", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_E.SNOOP_MISS", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x200080001", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts demand data reads", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_E.SNOOP_NONE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x80080001", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_F.ANY_SNOOP", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_F.ANY_SNOOP", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x3F80200001", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_F.HITM_OTHER_CORE", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_F.HITM_OTHER_CORE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x1000200001", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x800200001", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x400200001", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x100200001", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts demand data reads", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_F.SNOOP_MISS", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x200200001", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts demand data reads", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_F.SNOOP_NONE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x80200001", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_M.ANY_SNOOP", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_M.ANY_SNOOP", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x3F80040001", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_M.HITM_OTHER_CORE", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_M.HITM_OTHER_CORE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x1000040001", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x800040001", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x400040001", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x100040001", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts demand data reads", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_M.SNOOP_MISS", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x200040001", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts demand data reads", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_M.SNOOP_NONE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x80040001", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_S.ANY_SNOOP", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_S.ANY_SNOOP", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x3F80100001", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_S.HITM_OTHER_CORE", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_S.HITM_OTHER_CORE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x1000100001", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x800100001", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x400100001", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x100100001", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts demand data reads", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_S.SNOOP_MISS", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x200100001", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts demand data reads", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_S.SNOOP_NONE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x80100001", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT.ANY_SNOOP OCR.DEMAND_RFO.L3_HIT.ANY_SNOOP", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_RFO.L3_HIT.ANY_SNOOP", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x3F803C0002", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT.HITM_OTHER_CORE OCR.DEMAND_RFO.L3_HIT.HITM_OTHER_CORE", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_RFO.L3_HIT.HITM_OTHER_CORE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x10003C0002", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT.HIT_OTHER_CORE_FWD OCR.DEMAND_RFO.L3_HIT.HIT_OTHER_CORE_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_RFO.L3_HIT.HIT_OTHER_CORE_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x8003C0002", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.DEMAND_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x4003C0002", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT.NO_SNOOP_NEEDED OCR.DEMAND_RFO.L3_HIT.NO_SNOOP_NEEDED", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_RFO.L3_HIT.NO_SNOOP_NEEDED", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x1003C0002", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all demand data writes (RFOs)", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HIT_WITH_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x8007C0002", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT.SNOOP_MISS", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_MISS", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x2003C0002", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT.SNOOP_NONE", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_NONE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x803C0002", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_E.ANY_SNOOP", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_RFO.L3_HIT_E.ANY_SNOOP", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x3F80080002", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_E.HITM_OTHER_CORE", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_RFO.L3_HIT_E.HITM_OTHER_CORE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x1000080002", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x800080002", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x400080002", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_E.NO_SNOOP_NEEDED", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_RFO.L3_HIT_E.NO_SNOOP_NEEDED", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x100080002", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all demand data writes (RFOs)", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_RFO.L3_HIT_E.SNOOP_MISS", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x200080002", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all demand data writes (RFOs)", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_RFO.L3_HIT_E.SNOOP_NONE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x80080002", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_F.ANY_SNOOP", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_RFO.L3_HIT_F.ANY_SNOOP", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x3F80200002", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_F.HITM_OTHER_CORE", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_RFO.L3_HIT_F.HITM_OTHER_CORE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x1000200002", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x800200002", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x400200002", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_F.NO_SNOOP_NEEDED", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_RFO.L3_HIT_F.NO_SNOOP_NEEDED", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x100200002", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all demand data writes (RFOs)", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_RFO.L3_HIT_F.SNOOP_MISS", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x200200002", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all demand data writes (RFOs)", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_RFO.L3_HIT_F.SNOOP_NONE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x80200002", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_M.ANY_SNOOP", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_RFO.L3_HIT_M.ANY_SNOOP", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x3F80040002", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_M.HITM_OTHER_CORE", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_RFO.L3_HIT_M.HITM_OTHER_CORE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x1000040002", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x800040002", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x400040002", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_M.NO_SNOOP_NEEDED", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_RFO.L3_HIT_M.NO_SNOOP_NEEDED", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x100040002", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all demand data writes (RFOs)", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_RFO.L3_HIT_M.SNOOP_MISS", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x200040002", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all demand data writes (RFOs)", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_RFO.L3_HIT_M.SNOOP_NONE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x80040002", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_S.ANY_SNOOP", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_RFO.L3_HIT_S.ANY_SNOOP", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x3F80100002", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_S.HITM_OTHER_CORE", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_RFO.L3_HIT_S.HITM_OTHER_CORE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x1000100002", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x800100002", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x400100002", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_S.NO_SNOOP_NEEDED", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_RFO.L3_HIT_S.NO_SNOOP_NEEDED", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x100100002", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all demand data writes (RFOs)", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_RFO.L3_HIT_S.SNOOP_MISS", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x200100002", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all demand data writes (RFOs)", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_RFO.L3_HIT_S.SNOOP_NONE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x80100002", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT.ANY_SNOOP OCR.OTHER.L3_HIT.ANY_SNOOP", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.OTHER.L3_HIT.ANY_SNOOP", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x3F803C8000", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT.HITM_OTHER_CORE OCR.OTHER.L3_HIT.HITM_OTHER_CORE", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.OTHER.L3_HIT.HITM_OTHER_CORE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x10003C8000", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT.HIT_OTHER_CORE_FWD OCR.OTHER.L3_HIT.HIT_OTHER_CORE_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.OTHER.L3_HIT.HIT_OTHER_CORE_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x8003C8000", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.OTHER.L3_HIT.HIT_OTHER_CORE_NO_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.OTHER.L3_HIT.HIT_OTHER_CORE_NO_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x4003C8000", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT.NO_SNOOP_NEEDED OCR.OTHER.L3_HIT.NO_SNOOP_NEEDED", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.OTHER.L3_HIT.NO_SNOOP_NEEDED", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x1003C8000", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts any other requests", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.OTHER.L3_HIT.SNOOP_HIT_WITH_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x8007C8000", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT.SNOOP_MISS", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.OTHER.L3_HIT.SNOOP_MISS", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x2003C8000", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT.SNOOP_NONE", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.OTHER.L3_HIT.SNOOP_NONE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x803C8000", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_E.ANY_SNOOP", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.OTHER.L3_HIT_E.ANY_SNOOP", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x3F80088000", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_E.HITM_OTHER_CORE", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.OTHER.L3_HIT_E.HITM_OTHER_CORE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x1000088000", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_E.HIT_OTHER_CORE_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.OTHER.L3_HIT_E.HIT_OTHER_CORE_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x800088000", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.OTHER.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x400088000", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_E.NO_SNOOP_NEEDED", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.OTHER.L3_HIT_E.NO_SNOOP_NEEDED", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x100088000", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts any other requests", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.OTHER.L3_HIT_E.SNOOP_MISS", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x200088000", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts any other requests", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.OTHER.L3_HIT_E.SNOOP_NONE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x80088000", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_F.ANY_SNOOP", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.OTHER.L3_HIT_F.ANY_SNOOP", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x3F80208000", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_F.HITM_OTHER_CORE", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.OTHER.L3_HIT_F.HITM_OTHER_CORE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x1000208000", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_F.HIT_OTHER_CORE_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.OTHER.L3_HIT_F.HIT_OTHER_CORE_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x800208000", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.OTHER.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x400208000", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_F.NO_SNOOP_NEEDED", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.OTHER.L3_HIT_F.NO_SNOOP_NEEDED", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x100208000", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts any other requests", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.OTHER.L3_HIT_F.SNOOP_MISS", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x200208000", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts any other requests", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.OTHER.L3_HIT_F.SNOOP_NONE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x80208000", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_M.ANY_SNOOP", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.OTHER.L3_HIT_M.ANY_SNOOP", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x3F80048000", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_M.HITM_OTHER_CORE", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.OTHER.L3_HIT_M.HITM_OTHER_CORE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x1000048000", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_M.HIT_OTHER_CORE_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.OTHER.L3_HIT_M.HIT_OTHER_CORE_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x800048000", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.OTHER.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x400048000", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_M.NO_SNOOP_NEEDED", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.OTHER.L3_HIT_M.NO_SNOOP_NEEDED", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x100048000", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts any other requests", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.OTHER.L3_HIT_M.SNOOP_MISS", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x200048000", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts any other requests", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.OTHER.L3_HIT_M.SNOOP_NONE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x80048000", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_S.ANY_SNOOP", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.OTHER.L3_HIT_S.ANY_SNOOP", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x3F80108000", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_S.HITM_OTHER_CORE", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.OTHER.L3_HIT_S.HITM_OTHER_CORE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x1000108000", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_S.HIT_OTHER_CORE_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.OTHER.L3_HIT_S.HIT_OTHER_CORE_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x800108000", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.OTHER.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x400108000", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_S.NO_SNOOP_NEEDED", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.OTHER.L3_HIT_S.NO_SNOOP_NEEDED", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x100108000", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts any other requests", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.OTHER.L3_HIT_S.SNOOP_MISS", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x200108000", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts any other requests", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.OTHER.L3_HIT_S.SNOOP_NONE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x80108000", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT.ANY_SNOOP OCR.PF_L1D_AND_SW.L3_HIT.ANY_SNOOP", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L1D_AND_SW.L3_HIT.ANY_SNOOP", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x3F803C0400", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT.HITM_OTHER_CORE OCR.PF_L1D_AND_SW.L3_HIT.HITM_OTHER_CORE", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L1D_AND_SW.L3_HIT.HITM_OTHER_CORE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x10003C0400", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT.HIT_OTHER_CORE_FWD OCR.PF_L1D_AND_SW.L3_HIT.HIT_OTHER_CORE_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L1D_AND_SW.L3_HIT.HIT_OTHER_CORE_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x8003C0400", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.PF_L1D_AND_SW.L3_HIT.HIT_OTHER_CORE_NO_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L1D_AND_SW.L3_HIT.HIT_OTHER_CORE_NO_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x4003C0400", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT.NO_SNOOP_NEEDED OCR.PF_L1D_AND_SW.L3_HIT.NO_SNOOP_NEEDED", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L1D_AND_SW.L3_HIT.NO_SNOOP_NEEDED", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x1003C0400", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L1D_AND_SW.L3_HIT.SNOOP_HIT_WITH_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x8007C0400", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT.SNOOP_MISS", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L1D_AND_SW.L3_HIT.SNOOP_MISS", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x2003C0400", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT.SNOOP_NONE", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L1D_AND_SW.L3_HIT.SNOOP_NONE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x803C0400", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_E.ANY_SNOOP", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_E.ANY_SNOOP", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x3F80080400", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_E.HITM_OTHER_CORE", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_E.HITM_OTHER_CORE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x1000080400", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_E.HIT_OTHER_CORE_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_E.HIT_OTHER_CORE_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x800080400", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x400080400", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_E.NO_SNOOP_NEEDED", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_E.NO_SNOOP_NEEDED", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x100080400", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_E.SNOOP_MISS", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x200080400", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_E.SNOOP_NONE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x80080400", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_F.ANY_SNOOP", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_F.ANY_SNOOP", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x3F80200400", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_F.HITM_OTHER_CORE", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_F.HITM_OTHER_CORE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x1000200400", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_F.HIT_OTHER_CORE_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_F.HIT_OTHER_CORE_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x800200400", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x400200400", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_F.NO_SNOOP_NEEDED", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_F.NO_SNOOP_NEEDED", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x100200400", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_F.SNOOP_MISS", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x200200400", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_F.SNOOP_NONE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x80200400", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_M.ANY_SNOOP", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_M.ANY_SNOOP", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x3F80040400", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_M.HITM_OTHER_CORE", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_M.HITM_OTHER_CORE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x1000040400", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_M.HIT_OTHER_CORE_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_M.HIT_OTHER_CORE_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x800040400", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x400040400", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_M.NO_SNOOP_NEEDED", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_M.NO_SNOOP_NEEDED", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x100040400", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_M.SNOOP_MISS", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x200040400", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_M.SNOOP_NONE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x80040400", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_S.ANY_SNOOP", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_S.ANY_SNOOP", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x3F80100400", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_S.HITM_OTHER_CORE", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_S.HITM_OTHER_CORE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x1000100400", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_S.HIT_OTHER_CORE_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_S.HIT_OTHER_CORE_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x800100400", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x400100400", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_S.NO_SNOOP_NEEDED", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_S.NO_SNOOP_NEEDED", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x100100400", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_S.SNOOP_MISS", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x200100400", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_S.SNOOP_NONE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x80100400", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT.ANY_SNOOP OCR.PF_L2_DATA_RD.L3_HIT.ANY_SNOOP", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L2_DATA_RD.L3_HIT.ANY_SNOOP", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x3F803C0010", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT.HITM_OTHER_CORE OCR.PF_L2_DATA_RD.L3_HIT.HITM_OTHER_CORE", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L2_DATA_RD.L3_HIT.HITM_OTHER_CORE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x10003C0010", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD OCR.PF_L2_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L2_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x8003C0010", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.PF_L2_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L2_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x4003C0010", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT.NO_SNOOP_NEEDED OCR.PF_L2_DATA_RD.L3_HIT.NO_SNOOP_NEEDED", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L2_DATA_RD.L3_HIT.NO_SNOOP_NEEDED", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x1003C0010", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts prefetch (that bring data to L2) data reads", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L2_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x8007C0010", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT.SNOOP_MISS", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L2_DATA_RD.L3_HIT.SNOOP_MISS", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x2003C0010", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT.SNOOP_NONE", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L2_DATA_RD.L3_HIT.SNOOP_NONE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x803C0010", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_E.ANY_SNOOP", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_E.ANY_SNOOP", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x3F80080010", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_E.HITM_OTHER_CORE", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_E.HITM_OTHER_CORE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x1000080010", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x800080010", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x400080010", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x100080010", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts prefetch (that bring data to L2) data reads", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_E.SNOOP_MISS", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x200080010", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts prefetch (that bring data to L2) data reads", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_E.SNOOP_NONE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x80080010", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_F.ANY_SNOOP", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_F.ANY_SNOOP", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x3F80200010", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_F.HITM_OTHER_CORE", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_F.HITM_OTHER_CORE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x1000200010", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x800200010", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x400200010", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x100200010", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts prefetch (that bring data to L2) data reads", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_F.SNOOP_MISS", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x200200010", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts prefetch (that bring data to L2) data reads", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_F.SNOOP_NONE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x80200010", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_M.ANY_SNOOP", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_M.ANY_SNOOP", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x3F80040010", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_M.HITM_OTHER_CORE", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_M.HITM_OTHER_CORE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x1000040010", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x800040010", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x400040010", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x100040010", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts prefetch (that bring data to L2) data reads", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_M.SNOOP_MISS", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x200040010", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts prefetch (that bring data to L2) data reads", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_M.SNOOP_NONE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x80040010", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_S.ANY_SNOOP", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_S.ANY_SNOOP", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x3F80100010", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_S.HITM_OTHER_CORE", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_S.HITM_OTHER_CORE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x1000100010", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x800100010", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x400100010", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x100100010", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts prefetch (that bring data to L2) data reads", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_S.SNOOP_MISS", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x200100010", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts prefetch (that bring data to L2) data reads", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_S.SNOOP_NONE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x80100010", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT.ANY_SNOOP OCR.PF_L2_RFO.L3_HIT.ANY_SNOOP", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L2_RFO.L3_HIT.ANY_SNOOP", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x3F803C0020", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT.HITM_OTHER_CORE OCR.PF_L2_RFO.L3_HIT.HITM_OTHER_CORE", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L2_RFO.L3_HIT.HITM_OTHER_CORE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x10003C0020", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT.HIT_OTHER_CORE_FWD OCR.PF_L2_RFO.L3_HIT.HIT_OTHER_CORE_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L2_RFO.L3_HIT.HIT_OTHER_CORE_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x8003C0020", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.PF_L2_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L2_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x4003C0020", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT.NO_SNOOP_NEEDED OCR.PF_L2_RFO.L3_HIT.NO_SNOOP_NEEDED", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L2_RFO.L3_HIT.NO_SNOOP_NEEDED", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x1003C0020", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L2_RFO.L3_HIT.SNOOP_HIT_WITH_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x8007C0020", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT.SNOOP_MISS", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L2_RFO.L3_HIT.SNOOP_MISS", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x2003C0020", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT.SNOOP_NONE", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L2_RFO.L3_HIT.SNOOP_NONE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x803C0020", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_E.ANY_SNOOP", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L2_RFO.L3_HIT_E.ANY_SNOOP", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x3F80080020", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_E.HITM_OTHER_CORE", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L2_RFO.L3_HIT_E.HITM_OTHER_CORE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x1000080020", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L2_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x800080020", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L2_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x400080020", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_E.NO_SNOOP_NEEDED", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L2_RFO.L3_HIT_E.NO_SNOOP_NEEDED", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x100080020", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L2_RFO.L3_HIT_E.SNOOP_MISS", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x200080020", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L2_RFO.L3_HIT_E.SNOOP_NONE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x80080020", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_F.ANY_SNOOP", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L2_RFO.L3_HIT_F.ANY_SNOOP", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x3F80200020", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_F.HITM_OTHER_CORE", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L2_RFO.L3_HIT_F.HITM_OTHER_CORE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x1000200020", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L2_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x800200020", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L2_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x400200020", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_F.NO_SNOOP_NEEDED", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L2_RFO.L3_HIT_F.NO_SNOOP_NEEDED", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x100200020", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L2_RFO.L3_HIT_F.SNOOP_MISS", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x200200020", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L2_RFO.L3_HIT_F.SNOOP_NONE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x80200020", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_M.ANY_SNOOP", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L2_RFO.L3_HIT_M.ANY_SNOOP", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x3F80040020", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_M.HITM_OTHER_CORE", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L2_RFO.L3_HIT_M.HITM_OTHER_CORE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x1000040020", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L2_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x800040020", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L2_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x400040020", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_M.NO_SNOOP_NEEDED", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L2_RFO.L3_HIT_M.NO_SNOOP_NEEDED", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x100040020", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L2_RFO.L3_HIT_M.SNOOP_MISS", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x200040020", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L2_RFO.L3_HIT_M.SNOOP_NONE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x80040020", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_S.ANY_SNOOP", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L2_RFO.L3_HIT_S.ANY_SNOOP", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x3F80100020", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_S.HITM_OTHER_CORE", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L2_RFO.L3_HIT_S.HITM_OTHER_CORE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x1000100020", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L2_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x800100020", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L2_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x400100020", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_S.NO_SNOOP_NEEDED", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L2_RFO.L3_HIT_S.NO_SNOOP_NEEDED", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x100100020", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L2_RFO.L3_HIT_S.SNOOP_MISS", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x200100020", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L2_RFO.L3_HIT_S.SNOOP_NONE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x80100020", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT.ANY_SNOOP OCR.PF_L3_DATA_RD.L3_HIT.ANY_SNOOP", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L3_DATA_RD.L3_HIT.ANY_SNOOP", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x3F803C0080", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT.HITM_OTHER_CORE OCR.PF_L3_DATA_RD.L3_HIT.HITM_OTHER_CORE", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L3_DATA_RD.L3_HIT.HITM_OTHER_CORE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x10003C0080", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD OCR.PF_L3_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L3_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x8003C0080", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.PF_L3_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L3_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x4003C0080", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT.NO_SNOOP_NEEDED OCR.PF_L3_DATA_RD.L3_HIT.NO_SNOOP_NEEDED", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L3_DATA_RD.L3_HIT.NO_SNOOP_NEEDED", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x1003C0080", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L3_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x8007C0080", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT.SNOOP_MISS", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L3_DATA_RD.L3_HIT.SNOOP_MISS", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x2003C0080", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT.SNOOP_NONE", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L3_DATA_RD.L3_HIT.SNOOP_NONE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x803C0080", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_E.ANY_SNOOP", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_E.ANY_SNOOP", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x3F80080080", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_E.HITM_OTHER_CORE", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_E.HITM_OTHER_CORE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x1000080080", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x800080080", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x400080080", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x100080080", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_E.SNOOP_MISS", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x200080080", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_E.SNOOP_NONE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x80080080", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_F.ANY_SNOOP", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_F.ANY_SNOOP", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x3F80200080", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_F.HITM_OTHER_CORE", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_F.HITM_OTHER_CORE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x1000200080", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x800200080", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x400200080", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x100200080", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_F.SNOOP_MISS", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x200200080", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_F.SNOOP_NONE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x80200080", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_M.ANY_SNOOP", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_M.ANY_SNOOP", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x3F80040080", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_M.HITM_OTHER_CORE", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_M.HITM_OTHER_CORE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x1000040080", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x800040080", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x400040080", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x100040080", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_M.SNOOP_MISS", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x200040080", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_M.SNOOP_NONE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x80040080", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_S.ANY_SNOOP", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_S.ANY_SNOOP", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x3F80100080", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_S.HITM_OTHER_CORE", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_S.HITM_OTHER_CORE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x1000100080", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x800100080", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x400100080", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x100100080", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_S.SNOOP_MISS", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x200100080", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_S.SNOOP_NONE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x80100080", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT.ANY_SNOOP OCR.PF_L3_RFO.L3_HIT.ANY_SNOOP", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L3_RFO.L3_HIT.ANY_SNOOP", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x3F803C0100", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT.HITM_OTHER_CORE OCR.PF_L3_RFO.L3_HIT.HITM_OTHER_CORE", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L3_RFO.L3_HIT.HITM_OTHER_CORE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x10003C0100", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT.HIT_OTHER_CORE_FWD OCR.PF_L3_RFO.L3_HIT.HIT_OTHER_CORE_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L3_RFO.L3_HIT.HIT_OTHER_CORE_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x8003C0100", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.PF_L3_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L3_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x4003C0100", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT.NO_SNOOP_NEEDED OCR.PF_L3_RFO.L3_HIT.NO_SNOOP_NEEDED", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L3_RFO.L3_HIT.NO_SNOOP_NEEDED", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x1003C0100", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L3_RFO.L3_HIT.SNOOP_HIT_WITH_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x8007C0100", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT.SNOOP_MISS", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L3_RFO.L3_HIT.SNOOP_MISS", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x2003C0100", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT.SNOOP_NONE", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L3_RFO.L3_HIT.SNOOP_NONE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x803C0100", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_E.ANY_SNOOP", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L3_RFO.L3_HIT_E.ANY_SNOOP", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x3F80080100", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_E.HITM_OTHER_CORE", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L3_RFO.L3_HIT_E.HITM_OTHER_CORE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x1000080100", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L3_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x800080100", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L3_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x400080100", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_E.NO_SNOOP_NEEDED", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L3_RFO.L3_HIT_E.NO_SNOOP_NEEDED", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x100080100", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L3_RFO.L3_HIT_E.SNOOP_MISS", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x200080100", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L3_RFO.L3_HIT_E.SNOOP_NONE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x80080100", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_F.ANY_SNOOP", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L3_RFO.L3_HIT_F.ANY_SNOOP", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x3F80200100", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_F.HITM_OTHER_CORE", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L3_RFO.L3_HIT_F.HITM_OTHER_CORE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x1000200100", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L3_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x800200100", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L3_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x400200100", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_F.NO_SNOOP_NEEDED", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L3_RFO.L3_HIT_F.NO_SNOOP_NEEDED", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x100200100", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L3_RFO.L3_HIT_F.SNOOP_MISS", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x200200100", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L3_RFO.L3_HIT_F.SNOOP_NONE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x80200100", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_M.ANY_SNOOP", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L3_RFO.L3_HIT_M.ANY_SNOOP", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x3F80040100", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_M.HITM_OTHER_CORE", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L3_RFO.L3_HIT_M.HITM_OTHER_CORE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x1000040100", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L3_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x800040100", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L3_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x400040100", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_M.NO_SNOOP_NEEDED", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L3_RFO.L3_HIT_M.NO_SNOOP_NEEDED", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x100040100", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L3_RFO.L3_HIT_M.SNOOP_MISS", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x200040100", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L3_RFO.L3_HIT_M.SNOOP_NONE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x80040100", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_S.ANY_SNOOP", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L3_RFO.L3_HIT_S.ANY_SNOOP", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x3F80100100", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_S.HITM_OTHER_CORE", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L3_RFO.L3_HIT_S.HITM_OTHER_CORE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x1000100100", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L3_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x800100100", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L3_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x400100100", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_S.NO_SNOOP_NEEDED", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L3_RFO.L3_HIT_S.NO_SNOOP_NEEDED", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x100100100", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L3_RFO.L3_HIT_S.SNOOP_MISS", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x200100100", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L3_RFO.L3_HIT_S.SNOOP_NONE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x80100100", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > { > "BriefDescription": "Demand and prefetch data reads", > "Counter": "0,1,2,3", > @@ -9987,5 +16539,41 @@ > "PublicDescription": "Counts the number of cache line split locks sent to the uncore.", > "SampleAfterValue": "100003", > "UMask": "0x10" > + }, > + { > + "BriefDescription": "Number of PREFETCHNTA instructions executed.", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3,4,5,6,7", > + "EventCode": "0x32", > + "EventName": "SW_PREFETCH_ACCESS.NTA", > + "SampleAfterValue": "2000003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Number of PREFETCHW instructions executed.", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3,4,5,6,7", > + "EventCode": "0x32", > + "EventName": "SW_PREFETCH_ACCESS.PREFETCHW", > + "SampleAfterValue": "2000003", > + "UMask": "0x8" > + }, > + { > + "BriefDescription": "Number of PREFETCHT0 instructions executed.", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3,4,5,6,7", > + "EventCode": "0x32", > + "EventName": "SW_PREFETCH_ACCESS.T0", > + "SampleAfterValue": "2000003", > + "UMask": "0x2" > + }, > + { > + "BriefDescription": "Number of PREFETCHT1 or PREFETCHT2 instructions executed.", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3,4,5,6,7", > + "EventCode": "0x32", > + "EventName": "SW_PREFETCH_ACCESS.T1_T2", > + "SampleAfterValue": "2000003", > + "UMask": "0x4" > } > ] > \ No newline at end of file > diff --git a/tools/perf/pmu-events/arch/x86/cascadelakex/other.json b/tools/perf/pmu-events/arch/x86/cascadelakex/other.json > index d8b145a7d303..bb23a91b0127 100644 > --- a/tools/perf/pmu-events/arch/x86/cascadelakex/other.json > +++ b/tools/perf/pmu-events/arch/x86/cascadelakex/other.json > @@ -83,8411 +83,1859 @@ > "UMask": "0x1" > }, > { > - "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT.ANY_SNOOP OCR.ALL_DATA_RD.L3_HIT.ANY_SNOOP OCR.ALL_DATA_RD.L3_HIT.ANY_SNOOP", > + "BriefDescription": "OCR.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP OCR.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_DATA_RD.L3_HIT.ANY_SNOOP", > + "EventName": "OCR.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x3F803C0491", > + "MSRValue": "0x3F80400491", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT.HITM_OTHER_CORE OCR.ALL_DATA_RD.L3_HIT.HITM_OTHER_CORE OCR.ALL_DATA_RD.L3_HIT.HITM_OTHER_CORE", > + "BriefDescription": "OCR.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE OCR.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_DATA_RD.L3_HIT.HITM_OTHER_CORE", > + "EventName": "OCR.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x10003C0491", > + "MSRValue": "0x80400491", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD OCR.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD OCR.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD", > + "BriefDescription": "OCR.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED OCR.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD", > + "EventName": "OCR.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x8003C0491", > + "MSRValue": "0x100400491", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", > + "BriefDescription": "OCR.ALL_DATA_RD.SUPPLIER_NONE.ANY_SNOOP OCR.ALL_DATA_RD.SUPPLIER_NONE.ANY_SNOOP", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", > + "EventName": "OCR.ALL_DATA_RD.SUPPLIER_NONE.ANY_SNOOP", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x4003C0491", > + "MSRValue": "0x3F80020491", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT.NO_SNOOP_NEEDED OCR.ALL_DATA_RD.L3_HIT.NO_SNOOP_NEEDED OCR.ALL_DATA_RD.L3_HIT.NO_SNOOP_NEEDED", > + "BriefDescription": "OCR.ALL_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE OCR.ALL_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_DATA_RD.L3_HIT.NO_SNOOP_NEEDED", > + "EventName": "OCR.ALL_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x1003C0491", > + "MSRValue": "0x1000020491", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", > + "BriefDescription": "OCR.ALL_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD OCR.ALL_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", > + "EventName": "OCR.ALL_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x8007C0491", > + "MSRValue": "0x800020491", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT.SNOOP_MISS OCR.ALL_DATA_RD.L3_HIT.SNOOP_MISS", > + "BriefDescription": "OCR.ALL_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD OCR.ALL_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_DATA_RD.L3_HIT.SNOOP_MISS", > + "EventName": "OCR.ALL_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x2003C0491", > + "MSRValue": "0x400020491", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT.SNOOP_NONE OCR.ALL_DATA_RD.L3_HIT.SNOOP_NONE", > + "BriefDescription": "OCR.ALL_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED OCR.ALL_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_DATA_RD.L3_HIT.SNOOP_NONE", > + "EventName": "OCR.ALL_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x803C0491", > + "MSRValue": "0x100020491", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_E.ANY_SNOOP OCR.ALL_DATA_RD.L3_HIT_E.ANY_SNOOP", > + "BriefDescription": "OCR.ALL_DATA_RD.SUPPLIER_NONE.SNOOP_MISS", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_DATA_RD.L3_HIT_E.ANY_SNOOP", > + "EventName": "OCR.ALL_DATA_RD.SUPPLIER_NONE.SNOOP_MISS", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x3F80080491", > + "MSRValue": "0x200020491", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_E.HITM_OTHER_CORE OCR.ALL_DATA_RD.L3_HIT_E.HITM_OTHER_CORE", > + "BriefDescription": "OCR.ALL_DATA_RD.SUPPLIER_NONE.SNOOP_NONE", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_DATA_RD.L3_HIT_E.HITM_OTHER_CORE", > + "EventName": "OCR.ALL_DATA_RD.SUPPLIER_NONE.SNOOP_NONE", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x1000080491", > + "MSRValue": "0x80020491", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD OCR.ALL_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD", > + "BriefDescription": "OCR.ALL_PF_DATA_RD.ANY_RESPONSE have any response type.", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD", > + "EventName": "OCR.ALL_PF_DATA_RD.ANY_RESPONSE", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x800080491", > + "MSRValue": "0x10490", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD OCR.ALL_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", > + "BriefDescription": "OCR.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP OCR.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", > + "EventName": "OCR.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x400080491", > + "MSRValue": "0x3F80400490", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED OCR.ALL_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED", > + "BriefDescription": "OCR.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE OCR.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED", > + "EventName": "OCR.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x100080491", > + "MSRValue": "0x80400490", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_E.SNOOP_MISS", > + "BriefDescription": "OCR.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED OCR.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_DATA_RD.L3_HIT_E.SNOOP_MISS", > + "EventName": "OCR.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x200080491", > + "MSRValue": "0x100400490", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_E.SNOOP_NONE", > + "BriefDescription": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.ANY_SNOOP OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.ANY_SNOOP", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_DATA_RD.L3_HIT_E.SNOOP_NONE", > + "EventName": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.ANY_SNOOP", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x80080491", > + "MSRValue": "0x3F80020490", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_F.ANY_SNOOP OCR.ALL_DATA_RD.L3_HIT_F.ANY_SNOOP", > + "BriefDescription": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_DATA_RD.L3_HIT_F.ANY_SNOOP", > + "EventName": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x3F80200491", > + "MSRValue": "0x1000020490", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_F.HITM_OTHER_CORE OCR.ALL_DATA_RD.L3_HIT_F.HITM_OTHER_CORE", > + "BriefDescription": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_DATA_RD.L3_HIT_F.HITM_OTHER_CORE", > + "EventName": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x1000200491", > + "MSRValue": "0x800020490", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD OCR.ALL_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD", > + "BriefDescription": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD", > + "EventName": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x800200491", > + "MSRValue": "0x400020490", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD OCR.ALL_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", > + "BriefDescription": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", > + "EventName": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x400200491", > + "MSRValue": "0x100020490", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED OCR.ALL_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED", > + "BriefDescription": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.SNOOP_MISS", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED", > + "EventName": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.SNOOP_MISS", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x100200491", > + "MSRValue": "0x200020490", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_F.SNOOP_MISS", > + "BriefDescription": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.SNOOP_NONE", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_DATA_RD.L3_HIT_F.SNOOP_MISS", > + "EventName": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.SNOOP_NONE", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x200200491", > + "MSRValue": "0x80020490", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_F.SNOOP_NONE", > + "BriefDescription": "OCR.ALL_PF_RFO.ANY_RESPONSE have any response type.", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_DATA_RD.L3_HIT_F.SNOOP_NONE", > + "EventName": "OCR.ALL_PF_RFO.ANY_RESPONSE", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x80200491", > + "MSRValue": "0x10120", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_M.ANY_SNOOP OCR.ALL_DATA_RD.L3_HIT_M.ANY_SNOOP", > + "BriefDescription": "OCR.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP OCR.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_DATA_RD.L3_HIT_M.ANY_SNOOP", > + "EventName": "OCR.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x3F80040491", > + "MSRValue": "0x3F80400120", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_M.HITM_OTHER_CORE OCR.ALL_DATA_RD.L3_HIT_M.HITM_OTHER_CORE", > + "BriefDescription": "OCR.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE OCR.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_DATA_RD.L3_HIT_M.HITM_OTHER_CORE", > + "EventName": "OCR.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x1000040491", > + "MSRValue": "0x80400120", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD OCR.ALL_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD", > + "BriefDescription": "OCR.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED OCR.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD", > + "EventName": "OCR.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x800040491", > + "MSRValue": "0x100400120", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD OCR.ALL_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", > + "BriefDescription": "OCR.ALL_PF_RFO.SUPPLIER_NONE.ANY_SNOOP OCR.ALL_PF_RFO.SUPPLIER_NONE.ANY_SNOOP", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", > + "EventName": "OCR.ALL_PF_RFO.SUPPLIER_NONE.ANY_SNOOP", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x400040491", > + "MSRValue": "0x3F80020120", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED OCR.ALL_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED", > + "BriefDescription": "OCR.ALL_PF_RFO.SUPPLIER_NONE.HITM_OTHER_CORE OCR.ALL_PF_RFO.SUPPLIER_NONE.HITM_OTHER_CORE", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED", > + "EventName": "OCR.ALL_PF_RFO.SUPPLIER_NONE.HITM_OTHER_CORE", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x100040491", > + "MSRValue": "0x1000020120", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_M.SNOOP_MISS", > + "BriefDescription": "OCR.ALL_PF_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD OCR.ALL_PF_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_DATA_RD.L3_HIT_M.SNOOP_MISS", > + "EventName": "OCR.ALL_PF_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x200040491", > + "MSRValue": "0x800020120", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_M.SNOOP_NONE", > + "BriefDescription": "OCR.ALL_PF_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_DATA_RD.L3_HIT_M.SNOOP_NONE", > + "EventName": "OCR.ALL_PF_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x80040491", > + "MSRValue": "0x400020120", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_S.ANY_SNOOP OCR.ALL_DATA_RD.L3_HIT_S.ANY_SNOOP", > + "BriefDescription": "OCR.ALL_PF_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED OCR.ALL_PF_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_DATA_RD.L3_HIT_S.ANY_SNOOP", > + "EventName": "OCR.ALL_PF_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x3F80100491", > + "MSRValue": "0x100020120", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_S.HITM_OTHER_CORE OCR.ALL_DATA_RD.L3_HIT_S.HITM_OTHER_CORE", > + "BriefDescription": "OCR.ALL_PF_RFO.SUPPLIER_NONE.SNOOP_MISS", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_DATA_RD.L3_HIT_S.HITM_OTHER_CORE", > + "EventName": "OCR.ALL_PF_RFO.SUPPLIER_NONE.SNOOP_MISS", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x1000100491", > + "MSRValue": "0x200020120", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD OCR.ALL_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD", > + "BriefDescription": "OCR.ALL_PF_RFO.SUPPLIER_NONE.SNOOP_NONE", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD", > + "EventName": "OCR.ALL_PF_RFO.SUPPLIER_NONE.SNOOP_NONE", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x800100491", > + "MSRValue": "0x80020120", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD OCR.ALL_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", > + "BriefDescription": "OCR.ALL_READS.ANY_RESPONSE have any response type.", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", > + "EventName": "OCR.ALL_READS.ANY_RESPONSE", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x400100491", > + "MSRValue": "0x107F7", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED OCR.ALL_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED", > + "BriefDescription": "OCR.ALL_READS.PMM_HIT_LOCAL_PMM.ANY_SNOOP OCR.ALL_READS.PMM_HIT_LOCAL_PMM.ANY_SNOOP", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED", > + "EventName": "OCR.ALL_READS.PMM_HIT_LOCAL_PMM.ANY_SNOOP", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x100100491", > + "MSRValue": "0x3F804007F7", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_S.SNOOP_MISS", > + "BriefDescription": "OCR.ALL_READS.PMM_HIT_LOCAL_PMM.SNOOP_NONE OCR.ALL_READS.PMM_HIT_LOCAL_PMM.SNOOP_NONE", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_DATA_RD.L3_HIT_S.SNOOP_MISS", > + "EventName": "OCR.ALL_READS.PMM_HIT_LOCAL_PMM.SNOOP_NONE", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x200100491", > + "MSRValue": "0x804007F7", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_S.SNOOP_NONE", > + "BriefDescription": "OCR.ALL_READS.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED OCR.ALL_READS.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_DATA_RD.L3_HIT_S.SNOOP_NONE", > + "EventName": "OCR.ALL_READS.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x80100491", > + "MSRValue": "0x1004007F7", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "OCR.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP OCR.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP", > + "BriefDescription": "OCR.ALL_READS.SUPPLIER_NONE.ANY_SNOOP OCR.ALL_READS.SUPPLIER_NONE.ANY_SNOOP", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP", > + "EventName": "OCR.ALL_READS.SUPPLIER_NONE.ANY_SNOOP", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x3F80400491", > + "MSRValue": "0x3F800207F7", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "OCR.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE OCR.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE", > + "BriefDescription": "OCR.ALL_READS.SUPPLIER_NONE.HITM_OTHER_CORE OCR.ALL_READS.SUPPLIER_NONE.HITM_OTHER_CORE", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE", > + "EventName": "OCR.ALL_READS.SUPPLIER_NONE.HITM_OTHER_CORE", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x80400491", > + "MSRValue": "0x10000207F7", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "OCR.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED OCR.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", > + "BriefDescription": "OCR.ALL_READS.SUPPLIER_NONE.HIT_OTHER_CORE_FWD OCR.ALL_READS.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", > + "EventName": "OCR.ALL_READS.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x100400491", > + "MSRValue": "0x8000207F7", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "OCR.ALL_DATA_RD.SUPPLIER_NONE.ANY_SNOOP OCR.ALL_DATA_RD.SUPPLIER_NONE.ANY_SNOOP", > + "BriefDescription": "OCR.ALL_READS.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD OCR.ALL_READS.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_DATA_RD.SUPPLIER_NONE.ANY_SNOOP", > + "EventName": "OCR.ALL_READS.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x3F80020491", > + "MSRValue": "0x4000207F7", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "OCR.ALL_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE OCR.ALL_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE", > + "BriefDescription": "OCR.ALL_READS.SUPPLIER_NONE.NO_SNOOP_NEEDED OCR.ALL_READS.SUPPLIER_NONE.NO_SNOOP_NEEDED", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE", > + "EventName": "OCR.ALL_READS.SUPPLIER_NONE.NO_SNOOP_NEEDED", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x1000020491", > + "MSRValue": "0x1000207F7", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "OCR.ALL_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD OCR.ALL_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", > + "BriefDescription": "OCR.ALL_READS.SUPPLIER_NONE.SNOOP_MISS", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", > + "EventName": "OCR.ALL_READS.SUPPLIER_NONE.SNOOP_MISS", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x800020491", > + "MSRValue": "0x2000207F7", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "OCR.ALL_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD OCR.ALL_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", > + "BriefDescription": "OCR.ALL_READS.SUPPLIER_NONE.SNOOP_NONE", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", > + "EventName": "OCR.ALL_READS.SUPPLIER_NONE.SNOOP_NONE", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x400020491", > + "MSRValue": "0x800207F7", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "OCR.ALL_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED OCR.ALL_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED", > + "BriefDescription": "OCR.ALL_RFO.ANY_RESPONSE have any response type.", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED", > + "EventName": "OCR.ALL_RFO.ANY_RESPONSE", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x100020491", > + "MSRValue": "0x10122", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "OCR.ALL_DATA_RD.SUPPLIER_NONE.SNOOP_MISS", > + "BriefDescription": "OCR.ALL_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP OCR.ALL_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_DATA_RD.SUPPLIER_NONE.SNOOP_MISS", > + "EventName": "OCR.ALL_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x200020491", > + "MSRValue": "0x3F80400122", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "OCR.ALL_DATA_RD.SUPPLIER_NONE.SNOOP_NONE", > + "BriefDescription": "OCR.ALL_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE OCR.ALL_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_DATA_RD.SUPPLIER_NONE.SNOOP_NONE", > + "EventName": "OCR.ALL_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x80020491", > + "MSRValue": "0x80400122", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "OCR.ALL_PF_DATA_RD.ANY_RESPONSE have any response type.", > + "BriefDescription": "OCR.ALL_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED OCR.ALL_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_PF_DATA_RD.ANY_RESPONSE", > + "EventName": "OCR.ALL_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x10490", > + "MSRValue": "0x100400122", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT.ANY_SNOOP OCR.ALL_PF_DATA_RD.L3_HIT.ANY_SNOOP OCR.ALL_PF_DATA_RD.L3_HIT.ANY_SNOOP", > + "BriefDescription": "OCR.ALL_RFO.SUPPLIER_NONE.ANY_SNOOP OCR.ALL_RFO.SUPPLIER_NONE.ANY_SNOOP", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT.ANY_SNOOP", > + "EventName": "OCR.ALL_RFO.SUPPLIER_NONE.ANY_SNOOP", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x3F803C0490", > + "MSRValue": "0x3F80020122", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT.HITM_OTHER_CORE OCR.ALL_PF_DATA_RD.L3_HIT.HITM_OTHER_CORE OCR.ALL_PF_DATA_RD.L3_HIT.HITM_OTHER_CORE", > + "BriefDescription": "OCR.ALL_RFO.SUPPLIER_NONE.HITM_OTHER_CORE OCR.ALL_RFO.SUPPLIER_NONE.HITM_OTHER_CORE", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT.HITM_OTHER_CORE", > + "EventName": "OCR.ALL_RFO.SUPPLIER_NONE.HITM_OTHER_CORE", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x10003C0490", > + "MSRValue": "0x1000020122", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD OCR.ALL_PF_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD OCR.ALL_PF_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD", > + "BriefDescription": "OCR.ALL_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD OCR.ALL_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD", > + "EventName": "OCR.ALL_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x8003C0490", > + "MSRValue": "0x800020122", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", > + "BriefDescription": "OCR.ALL_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD OCR.ALL_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", > + "EventName": "OCR.ALL_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x4003C0490", > + "MSRValue": "0x400020122", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT.NO_SNOOP_NEEDED OCR.ALL_PF_DATA_RD.L3_HIT.NO_SNOOP_NEEDED OCR.ALL_PF_DATA_RD.L3_HIT.NO_SNOOP_NEEDED", > + "BriefDescription": "OCR.ALL_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED OCR.ALL_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT.NO_SNOOP_NEEDED", > + "EventName": "OCR.ALL_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x1003C0490", > + "MSRValue": "0x100020122", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", > + "BriefDescription": "OCR.ALL_RFO.SUPPLIER_NONE.SNOOP_MISS", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", > + "EventName": "OCR.ALL_RFO.SUPPLIER_NONE.SNOOP_MISS", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x8007C0490", > + "MSRValue": "0x200020122", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT.SNOOP_MISS OCR.ALL_PF_DATA_RD.L3_HIT.SNOOP_MISS", > + "BriefDescription": "OCR.ALL_RFO.SUPPLIER_NONE.SNOOP_NONE", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT.SNOOP_MISS", > + "EventName": "OCR.ALL_RFO.SUPPLIER_NONE.SNOOP_NONE", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x2003C0490", > + "MSRValue": "0x80020122", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT.SNOOP_NONE OCR.ALL_PF_DATA_RD.L3_HIT.SNOOP_NONE", > + "BriefDescription": "Counts all demand code reads have any response type.", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT.SNOOP_NONE", > + "EventName": "OCR.DEMAND_CODE_RD.ANY_RESPONSE", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x803C0490", > + "MSRValue": "0x10004", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_E.ANY_SNOOP OCR.ALL_PF_DATA_RD.L3_HIT_E.ANY_SNOOP", > + "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_E.ANY_SNOOP", > + "EventName": "OCR.DEMAND_CODE_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x3F80080490", > + "MSRValue": "0x3F80400004", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_E.HITM_OTHER_CORE OCR.ALL_PF_DATA_RD.L3_HIT_E.HITM_OTHER_CORE", > + "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_E.HITM_OTHER_CORE", > + "EventName": "OCR.DEMAND_CODE_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x1000080490", > + "MSRValue": "0x80400004", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD OCR.ALL_PF_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD", > + "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD", > + "EventName": "OCR.DEMAND_CODE_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x800080490", > + "MSRValue": "0x100400004", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", > + "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.SUPPLIER_NONE.ANY_SNOOP", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", > + "EventName": "OCR.DEMAND_CODE_RD.SUPPLIER_NONE.ANY_SNOOP", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x400080490", > + "MSRValue": "0x3F80020004", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED OCR.ALL_PF_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED", > + "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.SUPPLIER_NONE.HITM_OTHER_CORE", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED", > + "EventName": "OCR.DEMAND_CODE_RD.SUPPLIER_NONE.HITM_OTHER_CORE", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x100080490", > + "MSRValue": "0x1000020004", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_E.SNOOP_MISS", > + "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_E.SNOOP_MISS", > + "EventName": "OCR.DEMAND_CODE_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x200080490", > + "MSRValue": "0x800020004", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_E.SNOOP_NONE", > + "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_E.SNOOP_NONE", > + "EventName": "OCR.DEMAND_CODE_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x80080490", > + "MSRValue": "0x400020004", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_F.ANY_SNOOP OCR.ALL_PF_DATA_RD.L3_HIT_F.ANY_SNOOP", > + "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_F.ANY_SNOOP", > + "EventName": "OCR.DEMAND_CODE_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x3F80200490", > + "MSRValue": "0x100020004", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_F.HITM_OTHER_CORE OCR.ALL_PF_DATA_RD.L3_HIT_F.HITM_OTHER_CORE", > + "BriefDescription": "Counts all demand code reads", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_F.HITM_OTHER_CORE", > + "EventName": "OCR.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_MISS", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x1000200490", > + "MSRValue": "0x200020004", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD OCR.ALL_PF_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD", > + "BriefDescription": "Counts all demand code reads", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD", > + "EventName": "OCR.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_NONE", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x800200490", > + "MSRValue": "0x80020004", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", > + "BriefDescription": "Counts demand data reads have any response type.", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", > + "EventName": "OCR.DEMAND_DATA_RD.ANY_RESPONSE", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x400200490", > + "MSRValue": "0x10001", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED OCR.ALL_PF_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED", > + "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED", > + "EventName": "OCR.DEMAND_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x100200490", > + "MSRValue": "0x3F80400001", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_F.SNOOP_MISS", > + "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_F.SNOOP_MISS", > + "EventName": "OCR.DEMAND_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x200200490", > + "MSRValue": "0x80400001", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_F.SNOOP_NONE", > + "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_F.SNOOP_NONE", > + "EventName": "OCR.DEMAND_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x80200490", > + "MSRValue": "0x100400001", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_M.ANY_SNOOP OCR.ALL_PF_DATA_RD.L3_HIT_M.ANY_SNOOP", > + "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.SUPPLIER_NONE.ANY_SNOOP", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_M.ANY_SNOOP", > + "EventName": "OCR.DEMAND_DATA_RD.SUPPLIER_NONE.ANY_SNOOP", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x3F80040490", > + "MSRValue": "0x3F80020001", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_M.HITM_OTHER_CORE OCR.ALL_PF_DATA_RD.L3_HIT_M.HITM_OTHER_CORE", > + "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_M.HITM_OTHER_CORE", > + "EventName": "OCR.DEMAND_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x1000040490", > + "MSRValue": "0x1000020001", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD OCR.ALL_PF_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD", > + "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD", > + "EventName": "OCR.DEMAND_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x800040490", > + "MSRValue": "0x800020001", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", > + "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", > + "EventName": "OCR.DEMAND_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x400040490", > + "MSRValue": "0x400020001", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED OCR.ALL_PF_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED", > + "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED", > + "EventName": "OCR.DEMAND_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x100040490", > + "MSRValue": "0x100020001", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_M.SNOOP_MISS", > + "BriefDescription": "Counts demand data reads", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_M.SNOOP_MISS", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x200040490", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_M.SNOOP_NONE", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_M.SNOOP_NONE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x80040490", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_S.ANY_SNOOP OCR.ALL_PF_DATA_RD.L3_HIT_S.ANY_SNOOP", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_S.ANY_SNOOP", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x3F80100490", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_S.HITM_OTHER_CORE OCR.ALL_PF_DATA_RD.L3_HIT_S.HITM_OTHER_CORE", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_S.HITM_OTHER_CORE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x1000100490", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD OCR.ALL_PF_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x800100490", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x400100490", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED OCR.ALL_PF_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x100100490", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_S.SNOOP_MISS", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_S.SNOOP_MISS", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x200100490", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_S.SNOOP_NONE", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_S.SNOOP_NONE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x80100490", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP OCR.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x3F80400490", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE OCR.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x80400490", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED OCR.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x100400490", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.ANY_SNOOP OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.ANY_SNOOP", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.ANY_SNOOP", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x3F80020490", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x1000020490", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x800020490", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x400020490", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x100020490", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.SNOOP_MISS", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.SNOOP_MISS", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x200020490", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.SNOOP_NONE", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.SNOOP_NONE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x80020490", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_PF_RFO.ANY_RESPONSE have any response type.", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_PF_RFO.ANY_RESPONSE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x10120", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT.ANY_SNOOP OCR.ALL_PF_RFO.L3_HIT.ANY_SNOOP OCR.ALL_PF_RFO.L3_HIT.ANY_SNOOP", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_PF_RFO.L3_HIT.ANY_SNOOP", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x3F803C0120", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT.HITM_OTHER_CORE OCR.ALL_PF_RFO.L3_HIT.HITM_OTHER_CORE OCR.ALL_PF_RFO.L3_HIT.HITM_OTHER_CORE", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_PF_RFO.L3_HIT.HITM_OTHER_CORE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x10003C0120", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT.HIT_OTHER_CORE_FWD OCR.ALL_PF_RFO.L3_HIT.HIT_OTHER_CORE_FWD OCR.ALL_PF_RFO.L3_HIT.HIT_OTHER_CORE_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_PF_RFO.L3_HIT.HIT_OTHER_CORE_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x8003C0120", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_PF_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x4003C0120", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT.NO_SNOOP_NEEDED OCR.ALL_PF_RFO.L3_HIT.NO_SNOOP_NEEDED OCR.ALL_PF_RFO.L3_HIT.NO_SNOOP_NEEDED", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_PF_RFO.L3_HIT.NO_SNOOP_NEEDED", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x1003C0120", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT.SNOOP_HIT_WITH_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_PF_RFO.L3_HIT.SNOOP_HIT_WITH_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x8007C0120", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT.SNOOP_MISS OCR.ALL_PF_RFO.L3_HIT.SNOOP_MISS", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_PF_RFO.L3_HIT.SNOOP_MISS", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x2003C0120", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT.SNOOP_NONE OCR.ALL_PF_RFO.L3_HIT.SNOOP_NONE", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_PF_RFO.L3_HIT.SNOOP_NONE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x803C0120", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_E.ANY_SNOOP OCR.ALL_PF_RFO.L3_HIT_E.ANY_SNOOP", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_PF_RFO.L3_HIT_E.ANY_SNOOP", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x3F80080120", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_E.HITM_OTHER_CORE OCR.ALL_PF_RFO.L3_HIT_E.HITM_OTHER_CORE", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_PF_RFO.L3_HIT_E.HITM_OTHER_CORE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x1000080120", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD OCR.ALL_PF_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_PF_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x800080120", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_PF_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x400080120", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_E.NO_SNOOP_NEEDED OCR.ALL_PF_RFO.L3_HIT_E.NO_SNOOP_NEEDED", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_PF_RFO.L3_HIT_E.NO_SNOOP_NEEDED", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x100080120", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_E.SNOOP_MISS", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_PF_RFO.L3_HIT_E.SNOOP_MISS", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x200080120", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_E.SNOOP_NONE", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_PF_RFO.L3_HIT_E.SNOOP_NONE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x80080120", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_F.ANY_SNOOP OCR.ALL_PF_RFO.L3_HIT_F.ANY_SNOOP", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_PF_RFO.L3_HIT_F.ANY_SNOOP", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x3F80200120", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_F.HITM_OTHER_CORE OCR.ALL_PF_RFO.L3_HIT_F.HITM_OTHER_CORE", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_PF_RFO.L3_HIT_F.HITM_OTHER_CORE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x1000200120", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD OCR.ALL_PF_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_PF_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x800200120", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_PF_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x400200120", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_F.NO_SNOOP_NEEDED OCR.ALL_PF_RFO.L3_HIT_F.NO_SNOOP_NEEDED", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_PF_RFO.L3_HIT_F.NO_SNOOP_NEEDED", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x100200120", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_F.SNOOP_MISS", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_PF_RFO.L3_HIT_F.SNOOP_MISS", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x200200120", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_F.SNOOP_NONE", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_PF_RFO.L3_HIT_F.SNOOP_NONE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x80200120", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_M.ANY_SNOOP OCR.ALL_PF_RFO.L3_HIT_M.ANY_SNOOP", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_PF_RFO.L3_HIT_M.ANY_SNOOP", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x3F80040120", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_M.HITM_OTHER_CORE OCR.ALL_PF_RFO.L3_HIT_M.HITM_OTHER_CORE", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_PF_RFO.L3_HIT_M.HITM_OTHER_CORE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x1000040120", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD OCR.ALL_PF_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_PF_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x800040120", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_PF_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x400040120", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_M.NO_SNOOP_NEEDED OCR.ALL_PF_RFO.L3_HIT_M.NO_SNOOP_NEEDED", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_PF_RFO.L3_HIT_M.NO_SNOOP_NEEDED", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x100040120", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_M.SNOOP_MISS", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_PF_RFO.L3_HIT_M.SNOOP_MISS", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x200040120", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_M.SNOOP_NONE", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_PF_RFO.L3_HIT_M.SNOOP_NONE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x80040120", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_S.ANY_SNOOP OCR.ALL_PF_RFO.L3_HIT_S.ANY_SNOOP", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_PF_RFO.L3_HIT_S.ANY_SNOOP", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x3F80100120", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_S.HITM_OTHER_CORE OCR.ALL_PF_RFO.L3_HIT_S.HITM_OTHER_CORE", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_PF_RFO.L3_HIT_S.HITM_OTHER_CORE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x1000100120", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD OCR.ALL_PF_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_PF_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x800100120", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_PF_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x400100120", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_S.NO_SNOOP_NEEDED OCR.ALL_PF_RFO.L3_HIT_S.NO_SNOOP_NEEDED", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_PF_RFO.L3_HIT_S.NO_SNOOP_NEEDED", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x100100120", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_S.SNOOP_MISS", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_PF_RFO.L3_HIT_S.SNOOP_MISS", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x200100120", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_S.SNOOP_NONE", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_PF_RFO.L3_HIT_S.SNOOP_NONE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x80100120", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP OCR.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x3F80400120", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE OCR.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x80400120", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED OCR.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x100400120", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_PF_RFO.SUPPLIER_NONE.ANY_SNOOP OCR.ALL_PF_RFO.SUPPLIER_NONE.ANY_SNOOP", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_PF_RFO.SUPPLIER_NONE.ANY_SNOOP", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x3F80020120", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_PF_RFO.SUPPLIER_NONE.HITM_OTHER_CORE OCR.ALL_PF_RFO.SUPPLIER_NONE.HITM_OTHER_CORE", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_PF_RFO.SUPPLIER_NONE.HITM_OTHER_CORE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x1000020120", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_PF_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD OCR.ALL_PF_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_PF_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x800020120", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_PF_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_PF_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x400020120", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_PF_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED OCR.ALL_PF_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_PF_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x100020120", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_PF_RFO.SUPPLIER_NONE.SNOOP_MISS", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_PF_RFO.SUPPLIER_NONE.SNOOP_MISS", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x200020120", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_PF_RFO.SUPPLIER_NONE.SNOOP_NONE", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_PF_RFO.SUPPLIER_NONE.SNOOP_NONE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x80020120", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_READS.ANY_RESPONSE have any response type.", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_READS.ANY_RESPONSE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x107F7", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_READS.L3_HIT.ANY_SNOOP OCR.ALL_READS.L3_HIT.ANY_SNOOP OCR.ALL_READS.L3_HIT.ANY_SNOOP", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_READS.L3_HIT.ANY_SNOOP", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x3F803C07F7", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_READS.L3_HIT.HITM_OTHER_CORE OCR.ALL_READS.L3_HIT.HITM_OTHER_CORE OCR.ALL_READS.L3_HIT.HITM_OTHER_CORE", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_READS.L3_HIT.HITM_OTHER_CORE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x10003C07F7", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_READS.L3_HIT.HIT_OTHER_CORE_FWD OCR.ALL_READS.L3_HIT.HIT_OTHER_CORE_FWD OCR.ALL_READS.L3_HIT.HIT_OTHER_CORE_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_READS.L3_HIT.HIT_OTHER_CORE_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x8003C07F7", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_READS.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.ALL_READS.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.ALL_READS.L3_HIT.HIT_OTHER_CORE_NO_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_READS.L3_HIT.HIT_OTHER_CORE_NO_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x4003C07F7", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_READS.L3_HIT.NO_SNOOP_NEEDED OCR.ALL_READS.L3_HIT.NO_SNOOP_NEEDED OCR.ALL_READS.L3_HIT.NO_SNOOP_NEEDED", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_READS.L3_HIT.NO_SNOOP_NEEDED", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x1003C07F7", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_READS.L3_HIT.SNOOP_HIT_WITH_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_READS.L3_HIT.SNOOP_HIT_WITH_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x8007C07F7", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_READS.L3_HIT.SNOOP_MISS OCR.ALL_READS.L3_HIT.SNOOP_MISS", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_READS.L3_HIT.SNOOP_MISS", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x2003C07F7", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_READS.L3_HIT.SNOOP_NONE OCR.ALL_READS.L3_HIT.SNOOP_NONE", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_READS.L3_HIT.SNOOP_NONE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x803C07F7", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_READS.L3_HIT_E.ANY_SNOOP OCR.ALL_READS.L3_HIT_E.ANY_SNOOP", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_READS.L3_HIT_E.ANY_SNOOP", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x3F800807F7", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_READS.L3_HIT_E.HITM_OTHER_CORE OCR.ALL_READS.L3_HIT_E.HITM_OTHER_CORE", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_READS.L3_HIT_E.HITM_OTHER_CORE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x10000807F7", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_READS.L3_HIT_E.HIT_OTHER_CORE_FWD OCR.ALL_READS.L3_HIT_E.HIT_OTHER_CORE_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_READS.L3_HIT_E.HIT_OTHER_CORE_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x8000807F7", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_READS.L3_HIT_E.HIT_OTHER_CORE_NO_FWD OCR.ALL_READS.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_READS.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x4000807F7", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_READS.L3_HIT_E.NO_SNOOP_NEEDED OCR.ALL_READS.L3_HIT_E.NO_SNOOP_NEEDED", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_READS.L3_HIT_E.NO_SNOOP_NEEDED", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x1000807F7", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_READS.L3_HIT_E.SNOOP_MISS", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_READS.L3_HIT_E.SNOOP_MISS", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x2000807F7", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_READS.L3_HIT_E.SNOOP_NONE", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_READS.L3_HIT_E.SNOOP_NONE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x800807F7", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_READS.L3_HIT_F.ANY_SNOOP OCR.ALL_READS.L3_HIT_F.ANY_SNOOP", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_READS.L3_HIT_F.ANY_SNOOP", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x3F802007F7", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_READS.L3_HIT_F.HITM_OTHER_CORE OCR.ALL_READS.L3_HIT_F.HITM_OTHER_CORE", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_READS.L3_HIT_F.HITM_OTHER_CORE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x10002007F7", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_READS.L3_HIT_F.HIT_OTHER_CORE_FWD OCR.ALL_READS.L3_HIT_F.HIT_OTHER_CORE_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_READS.L3_HIT_F.HIT_OTHER_CORE_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x8002007F7", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_READS.L3_HIT_F.HIT_OTHER_CORE_NO_FWD OCR.ALL_READS.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_READS.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x4002007F7", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_READS.L3_HIT_F.NO_SNOOP_NEEDED OCR.ALL_READS.L3_HIT_F.NO_SNOOP_NEEDED", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_READS.L3_HIT_F.NO_SNOOP_NEEDED", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x1002007F7", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_READS.L3_HIT_F.SNOOP_MISS", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_READS.L3_HIT_F.SNOOP_MISS", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x2002007F7", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_READS.L3_HIT_F.SNOOP_NONE", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_READS.L3_HIT_F.SNOOP_NONE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x802007F7", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_READS.L3_HIT_M.ANY_SNOOP OCR.ALL_READS.L3_HIT_M.ANY_SNOOP", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_READS.L3_HIT_M.ANY_SNOOP", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x3F800407F7", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_READS.L3_HIT_M.HITM_OTHER_CORE OCR.ALL_READS.L3_HIT_M.HITM_OTHER_CORE", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_READS.L3_HIT_M.HITM_OTHER_CORE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x10000407F7", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_READS.L3_HIT_M.HIT_OTHER_CORE_FWD OCR.ALL_READS.L3_HIT_M.HIT_OTHER_CORE_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_READS.L3_HIT_M.HIT_OTHER_CORE_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x8000407F7", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_READS.L3_HIT_M.HIT_OTHER_CORE_NO_FWD OCR.ALL_READS.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_READS.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x4000407F7", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_READS.L3_HIT_M.NO_SNOOP_NEEDED OCR.ALL_READS.L3_HIT_M.NO_SNOOP_NEEDED", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_READS.L3_HIT_M.NO_SNOOP_NEEDED", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x1000407F7", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_READS.L3_HIT_M.SNOOP_MISS", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_READS.L3_HIT_M.SNOOP_MISS", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x2000407F7", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_READS.L3_HIT_M.SNOOP_NONE", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_READS.L3_HIT_M.SNOOP_NONE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x800407F7", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_READS.L3_HIT_S.ANY_SNOOP OCR.ALL_READS.L3_HIT_S.ANY_SNOOP", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_READS.L3_HIT_S.ANY_SNOOP", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x3F801007F7", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_READS.L3_HIT_S.HITM_OTHER_CORE OCR.ALL_READS.L3_HIT_S.HITM_OTHER_CORE", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_READS.L3_HIT_S.HITM_OTHER_CORE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x10001007F7", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_READS.L3_HIT_S.HIT_OTHER_CORE_FWD OCR.ALL_READS.L3_HIT_S.HIT_OTHER_CORE_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_READS.L3_HIT_S.HIT_OTHER_CORE_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x8001007F7", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_READS.L3_HIT_S.HIT_OTHER_CORE_NO_FWD OCR.ALL_READS.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_READS.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x4001007F7", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_READS.L3_HIT_S.NO_SNOOP_NEEDED OCR.ALL_READS.L3_HIT_S.NO_SNOOP_NEEDED", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_READS.L3_HIT_S.NO_SNOOP_NEEDED", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x1001007F7", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_READS.L3_HIT_S.SNOOP_MISS", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_READS.L3_HIT_S.SNOOP_MISS", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x2001007F7", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_READS.L3_HIT_S.SNOOP_NONE", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_READS.L3_HIT_S.SNOOP_NONE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x801007F7", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_READS.PMM_HIT_LOCAL_PMM.ANY_SNOOP OCR.ALL_READS.PMM_HIT_LOCAL_PMM.ANY_SNOOP", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_READS.PMM_HIT_LOCAL_PMM.ANY_SNOOP", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x3F804007F7", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_READS.PMM_HIT_LOCAL_PMM.SNOOP_NONE OCR.ALL_READS.PMM_HIT_LOCAL_PMM.SNOOP_NONE", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_READS.PMM_HIT_LOCAL_PMM.SNOOP_NONE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x804007F7", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_READS.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED OCR.ALL_READS.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_READS.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x1004007F7", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_READS.SUPPLIER_NONE.ANY_SNOOP OCR.ALL_READS.SUPPLIER_NONE.ANY_SNOOP", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_READS.SUPPLIER_NONE.ANY_SNOOP", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x3F800207F7", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_READS.SUPPLIER_NONE.HITM_OTHER_CORE OCR.ALL_READS.SUPPLIER_NONE.HITM_OTHER_CORE", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_READS.SUPPLIER_NONE.HITM_OTHER_CORE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x10000207F7", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_READS.SUPPLIER_NONE.HIT_OTHER_CORE_FWD OCR.ALL_READS.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_READS.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x8000207F7", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_READS.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD OCR.ALL_READS.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_READS.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x4000207F7", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_READS.SUPPLIER_NONE.NO_SNOOP_NEEDED OCR.ALL_READS.SUPPLIER_NONE.NO_SNOOP_NEEDED", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_READS.SUPPLIER_NONE.NO_SNOOP_NEEDED", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x1000207F7", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_READS.SUPPLIER_NONE.SNOOP_MISS", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_READS.SUPPLIER_NONE.SNOOP_MISS", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x2000207F7", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_READS.SUPPLIER_NONE.SNOOP_NONE", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_READS.SUPPLIER_NONE.SNOOP_NONE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x800207F7", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_RFO.ANY_RESPONSE have any response type.", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_RFO.ANY_RESPONSE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x10122", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_RFO.L3_HIT.ANY_SNOOP OCR.ALL_RFO.L3_HIT.ANY_SNOOP OCR.ALL_RFO.L3_HIT.ANY_SNOOP", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_RFO.L3_HIT.ANY_SNOOP", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x3F803C0122", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_RFO.L3_HIT.HITM_OTHER_CORE OCR.ALL_RFO.L3_HIT.HITM_OTHER_CORE OCR.ALL_RFO.L3_HIT.HITM_OTHER_CORE", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_RFO.L3_HIT.HITM_OTHER_CORE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x10003C0122", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_RFO.L3_HIT.HIT_OTHER_CORE_FWD OCR.ALL_RFO.L3_HIT.HIT_OTHER_CORE_FWD OCR.ALL_RFO.L3_HIT.HIT_OTHER_CORE_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_RFO.L3_HIT.HIT_OTHER_CORE_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x8003C0122", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.ALL_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.ALL_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x4003C0122", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_RFO.L3_HIT.NO_SNOOP_NEEDED OCR.ALL_RFO.L3_HIT.NO_SNOOP_NEEDED OCR.ALL_RFO.L3_HIT.NO_SNOOP_NEEDED", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_RFO.L3_HIT.NO_SNOOP_NEEDED", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x1003C0122", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_RFO.L3_HIT.SNOOP_HIT_WITH_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_RFO.L3_HIT.SNOOP_HIT_WITH_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x8007C0122", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_RFO.L3_HIT.SNOOP_MISS OCR.ALL_RFO.L3_HIT.SNOOP_MISS", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_RFO.L3_HIT.SNOOP_MISS", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x2003C0122", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_RFO.L3_HIT.SNOOP_NONE OCR.ALL_RFO.L3_HIT.SNOOP_NONE", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_RFO.L3_HIT.SNOOP_NONE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x803C0122", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_RFO.L3_HIT_E.ANY_SNOOP OCR.ALL_RFO.L3_HIT_E.ANY_SNOOP", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_RFO.L3_HIT_E.ANY_SNOOP", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x3F80080122", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_RFO.L3_HIT_E.HITM_OTHER_CORE OCR.ALL_RFO.L3_HIT_E.HITM_OTHER_CORE", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_RFO.L3_HIT_E.HITM_OTHER_CORE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x1000080122", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD OCR.ALL_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x800080122", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD OCR.ALL_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x400080122", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_RFO.L3_HIT_E.NO_SNOOP_NEEDED OCR.ALL_RFO.L3_HIT_E.NO_SNOOP_NEEDED", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_RFO.L3_HIT_E.NO_SNOOP_NEEDED", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x100080122", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_RFO.L3_HIT_E.SNOOP_MISS", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_RFO.L3_HIT_E.SNOOP_MISS", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x200080122", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_RFO.L3_HIT_E.SNOOP_NONE", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_RFO.L3_HIT_E.SNOOP_NONE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x80080122", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_RFO.L3_HIT_F.ANY_SNOOP OCR.ALL_RFO.L3_HIT_F.ANY_SNOOP", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_RFO.L3_HIT_F.ANY_SNOOP", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x3F80200122", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_RFO.L3_HIT_F.HITM_OTHER_CORE OCR.ALL_RFO.L3_HIT_F.HITM_OTHER_CORE", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_RFO.L3_HIT_F.HITM_OTHER_CORE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x1000200122", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD OCR.ALL_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x800200122", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD OCR.ALL_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x400200122", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_RFO.L3_HIT_F.NO_SNOOP_NEEDED OCR.ALL_RFO.L3_HIT_F.NO_SNOOP_NEEDED", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_RFO.L3_HIT_F.NO_SNOOP_NEEDED", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x100200122", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_RFO.L3_HIT_F.SNOOP_MISS", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_RFO.L3_HIT_F.SNOOP_MISS", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x200200122", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_RFO.L3_HIT_F.SNOOP_NONE", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_RFO.L3_HIT_F.SNOOP_NONE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x80200122", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_RFO.L3_HIT_M.ANY_SNOOP OCR.ALL_RFO.L3_HIT_M.ANY_SNOOP", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_RFO.L3_HIT_M.ANY_SNOOP", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x3F80040122", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_RFO.L3_HIT_M.HITM_OTHER_CORE OCR.ALL_RFO.L3_HIT_M.HITM_OTHER_CORE", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_RFO.L3_HIT_M.HITM_OTHER_CORE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x1000040122", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD OCR.ALL_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x800040122", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD OCR.ALL_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x400040122", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_RFO.L3_HIT_M.NO_SNOOP_NEEDED OCR.ALL_RFO.L3_HIT_M.NO_SNOOP_NEEDED", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_RFO.L3_HIT_M.NO_SNOOP_NEEDED", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x100040122", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_RFO.L3_HIT_M.SNOOP_MISS", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_RFO.L3_HIT_M.SNOOP_MISS", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x200040122", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_RFO.L3_HIT_M.SNOOP_NONE", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_RFO.L3_HIT_M.SNOOP_NONE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x80040122", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_RFO.L3_HIT_S.ANY_SNOOP OCR.ALL_RFO.L3_HIT_S.ANY_SNOOP", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_RFO.L3_HIT_S.ANY_SNOOP", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x3F80100122", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_RFO.L3_HIT_S.HITM_OTHER_CORE OCR.ALL_RFO.L3_HIT_S.HITM_OTHER_CORE", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_RFO.L3_HIT_S.HITM_OTHER_CORE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x1000100122", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD OCR.ALL_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x800100122", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD OCR.ALL_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x400100122", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_RFO.L3_HIT_S.NO_SNOOP_NEEDED OCR.ALL_RFO.L3_HIT_S.NO_SNOOP_NEEDED", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_RFO.L3_HIT_S.NO_SNOOP_NEEDED", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x100100122", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_RFO.L3_HIT_S.SNOOP_MISS", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_RFO.L3_HIT_S.SNOOP_MISS", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x200100122", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_RFO.L3_HIT_S.SNOOP_NONE", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_RFO.L3_HIT_S.SNOOP_NONE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x80100122", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP OCR.ALL_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x3F80400122", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE OCR.ALL_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x80400122", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED OCR.ALL_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x100400122", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_RFO.SUPPLIER_NONE.ANY_SNOOP OCR.ALL_RFO.SUPPLIER_NONE.ANY_SNOOP", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_RFO.SUPPLIER_NONE.ANY_SNOOP", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x3F80020122", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_RFO.SUPPLIER_NONE.HITM_OTHER_CORE OCR.ALL_RFO.SUPPLIER_NONE.HITM_OTHER_CORE", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_RFO.SUPPLIER_NONE.HITM_OTHER_CORE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x1000020122", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD OCR.ALL_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x800020122", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD OCR.ALL_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x400020122", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED OCR.ALL_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x100020122", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_RFO.SUPPLIER_NONE.SNOOP_MISS", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_RFO.SUPPLIER_NONE.SNOOP_MISS", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x200020122", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_RFO.SUPPLIER_NONE.SNOOP_NONE", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_RFO.SUPPLIER_NONE.SNOOP_NONE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x80020122", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all demand code reads have any response type.", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_CODE_RD.ANY_RESPONSE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x10004", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT.ANY_SNOOP OCR.DEMAND_CODE_RD.L3_HIT.ANY_SNOOP", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.ANY_SNOOP", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x3F803C0004", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT.HITM_OTHER_CORE OCR.DEMAND_CODE_RD.L3_HIT.HITM_OTHER_CORE", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.HITM_OTHER_CORE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x10003C0004", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT.HIT_OTHER_CORE_FWD OCR.DEMAND_CODE_RD.L3_HIT.HIT_OTHER_CORE_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.HIT_OTHER_CORE_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x8003C0004", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.DEMAND_CODE_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x4003C0004", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT.NO_SNOOP_NEEDED OCR.DEMAND_CODE_RD.L3_HIT.NO_SNOOP_NEEDED", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.NO_SNOOP_NEEDED", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x1003C0004", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all demand code reads", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_HIT_WITH_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x8007C0004", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_MISS", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_MISS", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x2003C0004", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_NONE", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_NONE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x803C0004", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_E.ANY_SNOOP", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_E.ANY_SNOOP", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x3F80080004", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_E.HITM_OTHER_CORE", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_E.HITM_OTHER_CORE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x1000080004", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_E.HIT_OTHER_CORE_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_E.HIT_OTHER_CORE_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x800080004", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x400080004", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_E.NO_SNOOP_NEEDED", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_E.NO_SNOOP_NEEDED", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x100080004", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all demand code reads", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_E.SNOOP_MISS", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x200080004", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all demand code reads", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_E.SNOOP_NONE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x80080004", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_F.ANY_SNOOP", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_F.ANY_SNOOP", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x3F80200004", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_F.HITM_OTHER_CORE", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_F.HITM_OTHER_CORE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x1000200004", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_F.HIT_OTHER_CORE_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_F.HIT_OTHER_CORE_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x800200004", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x400200004", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_F.NO_SNOOP_NEEDED", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_F.NO_SNOOP_NEEDED", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x100200004", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all demand code reads", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_F.SNOOP_MISS", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x200200004", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all demand code reads", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_F.SNOOP_NONE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x80200004", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_M.ANY_SNOOP", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_M.ANY_SNOOP", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x3F80040004", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_M.HITM_OTHER_CORE", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_M.HITM_OTHER_CORE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x1000040004", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_M.HIT_OTHER_CORE_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_M.HIT_OTHER_CORE_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x800040004", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x400040004", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_M.NO_SNOOP_NEEDED", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_M.NO_SNOOP_NEEDED", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x100040004", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all demand code reads", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_M.SNOOP_MISS", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x200040004", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all demand code reads", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_M.SNOOP_NONE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x80040004", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_S.ANY_SNOOP", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_S.ANY_SNOOP", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x3F80100004", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_S.HITM_OTHER_CORE", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_S.HITM_OTHER_CORE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x1000100004", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_S.HIT_OTHER_CORE_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_S.HIT_OTHER_CORE_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x800100004", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x400100004", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_S.NO_SNOOP_NEEDED", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_S.NO_SNOOP_NEEDED", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x100100004", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all demand code reads", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_S.SNOOP_MISS", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x200100004", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all demand code reads", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_S.SNOOP_NONE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x80100004", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_CODE_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x3F80400004", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_CODE_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x80400004", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_CODE_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x100400004", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.SUPPLIER_NONE.ANY_SNOOP", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_CODE_RD.SUPPLIER_NONE.ANY_SNOOP", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x3F80020004", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.SUPPLIER_NONE.HITM_OTHER_CORE", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_CODE_RD.SUPPLIER_NONE.HITM_OTHER_CORE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x1000020004", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_CODE_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x800020004", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_CODE_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x400020004", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_CODE_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x100020004", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all demand code reads", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_MISS", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x200020004", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all demand code reads", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_NONE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x80020004", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts demand data reads have any response type.", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_DATA_RD.ANY_RESPONSE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x10001", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT.ANY_SNOOP OCR.DEMAND_DATA_RD.L3_HIT.ANY_SNOOP", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.ANY_SNOOP", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x3F803C0001", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE OCR.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x10003C0001", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD OCR.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x8003C0001", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x4003C0001", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT.NO_SNOOP_NEEDED OCR.DEMAND_DATA_RD.L3_HIT.NO_SNOOP_NEEDED", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.NO_SNOOP_NEEDED", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x1003C0001", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts demand data reads", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x8007C0001", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_MISS", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_MISS", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x2003C0001", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_NONE", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_NONE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x803C0001", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_E.ANY_SNOOP", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_E.ANY_SNOOP", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x3F80080001", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_E.HITM_OTHER_CORE", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_E.HITM_OTHER_CORE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x1000080001", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x800080001", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x400080001", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x100080001", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts demand data reads", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_E.SNOOP_MISS", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x200080001", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts demand data reads", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_E.SNOOP_NONE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x80080001", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_F.ANY_SNOOP", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_F.ANY_SNOOP", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x3F80200001", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_F.HITM_OTHER_CORE", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_F.HITM_OTHER_CORE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x1000200001", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x800200001", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x400200001", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x100200001", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts demand data reads", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_F.SNOOP_MISS", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x200200001", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts demand data reads", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_F.SNOOP_NONE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x80200001", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_M.ANY_SNOOP", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_M.ANY_SNOOP", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x3F80040001", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_M.HITM_OTHER_CORE", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_M.HITM_OTHER_CORE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x1000040001", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x800040001", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x400040001", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x100040001", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts demand data reads", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_M.SNOOP_MISS", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x200040001", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts demand data reads", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_M.SNOOP_NONE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x80040001", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_S.ANY_SNOOP", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_S.ANY_SNOOP", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x3F80100001", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_S.HITM_OTHER_CORE", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_S.HITM_OTHER_CORE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x1000100001", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x800100001", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x400100001", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x100100001", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts demand data reads", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_S.SNOOP_MISS", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x200100001", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts demand data reads", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_S.SNOOP_NONE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x80100001", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x3F80400001", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x80400001", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x100400001", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.SUPPLIER_NONE.ANY_SNOOP", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_DATA_RD.SUPPLIER_NONE.ANY_SNOOP", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x3F80020001", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x1000020001", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x800020001", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x400020001", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x100020001", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts demand data reads", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_MISS", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x200020001", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts demand data reads", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_NONE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x80020001", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all demand data writes (RFOs) have any response type.", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_RFO.ANY_RESPONSE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x10002", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT.ANY_SNOOP OCR.DEMAND_RFO.L3_HIT.ANY_SNOOP", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_RFO.L3_HIT.ANY_SNOOP", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x3F803C0002", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT.HITM_OTHER_CORE OCR.DEMAND_RFO.L3_HIT.HITM_OTHER_CORE", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_RFO.L3_HIT.HITM_OTHER_CORE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x10003C0002", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT.HIT_OTHER_CORE_FWD OCR.DEMAND_RFO.L3_HIT.HIT_OTHER_CORE_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_RFO.L3_HIT.HIT_OTHER_CORE_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x8003C0002", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.DEMAND_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x4003C0002", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT.NO_SNOOP_NEEDED OCR.DEMAND_RFO.L3_HIT.NO_SNOOP_NEEDED", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_RFO.L3_HIT.NO_SNOOP_NEEDED", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x1003C0002", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all demand data writes (RFOs)", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HIT_WITH_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x8007C0002", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT.SNOOP_MISS", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_MISS", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x2003C0002", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT.SNOOP_NONE", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_NONE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x803C0002", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_E.ANY_SNOOP", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_RFO.L3_HIT_E.ANY_SNOOP", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x3F80080002", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_E.HITM_OTHER_CORE", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_RFO.L3_HIT_E.HITM_OTHER_CORE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x1000080002", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x800080002", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x400080002", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_E.NO_SNOOP_NEEDED", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_RFO.L3_HIT_E.NO_SNOOP_NEEDED", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x100080002", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all demand data writes (RFOs)", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_RFO.L3_HIT_E.SNOOP_MISS", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x200080002", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all demand data writes (RFOs)", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_RFO.L3_HIT_E.SNOOP_NONE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x80080002", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_F.ANY_SNOOP", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_RFO.L3_HIT_F.ANY_SNOOP", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x3F80200002", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_F.HITM_OTHER_CORE", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_RFO.L3_HIT_F.HITM_OTHER_CORE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x1000200002", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x800200002", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x400200002", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_F.NO_SNOOP_NEEDED", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_RFO.L3_HIT_F.NO_SNOOP_NEEDED", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x100200002", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all demand data writes (RFOs)", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_RFO.L3_HIT_F.SNOOP_MISS", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x200200002", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all demand data writes (RFOs)", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_RFO.L3_HIT_F.SNOOP_NONE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x80200002", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_M.ANY_SNOOP", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_RFO.L3_HIT_M.ANY_SNOOP", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x3F80040002", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_M.HITM_OTHER_CORE", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_RFO.L3_HIT_M.HITM_OTHER_CORE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x1000040002", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x800040002", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x400040002", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_M.NO_SNOOP_NEEDED", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_RFO.L3_HIT_M.NO_SNOOP_NEEDED", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x100040002", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all demand data writes (RFOs)", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_RFO.L3_HIT_M.SNOOP_MISS", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x200040002", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all demand data writes (RFOs)", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_RFO.L3_HIT_M.SNOOP_NONE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x80040002", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_S.ANY_SNOOP", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_RFO.L3_HIT_S.ANY_SNOOP", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x3F80100002", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_S.HITM_OTHER_CORE", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_RFO.L3_HIT_S.HITM_OTHER_CORE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x1000100002", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x800100002", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x400100002", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_S.NO_SNOOP_NEEDED", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_RFO.L3_HIT_S.NO_SNOOP_NEEDED", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x100100002", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all demand data writes (RFOs)", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_RFO.L3_HIT_S.SNOOP_MISS", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x200100002", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all demand data writes (RFOs)", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_RFO.L3_HIT_S.SNOOP_NONE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x80100002", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x3F80400002", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x80400002", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x100400002", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.SUPPLIER_NONE.ANY_SNOOP", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_RFO.SUPPLIER_NONE.ANY_SNOOP", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x3F80020002", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.SUPPLIER_NONE.HITM_OTHER_CORE", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_RFO.SUPPLIER_NONE.HITM_OTHER_CORE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x1000020002", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x800020002", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x400020002", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x100020002", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all demand data writes (RFOs)", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_RFO.SUPPLIER_NONE.SNOOP_MISS", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x200020002", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all demand data writes (RFOs)", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_RFO.SUPPLIER_NONE.SNOOP_NONE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x80020002", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts any other requests have any response type.", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.OTHER.ANY_RESPONSE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x18000", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT.ANY_SNOOP OCR.OTHER.L3_HIT.ANY_SNOOP", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.OTHER.L3_HIT.ANY_SNOOP", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x3F803C8000", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT.HITM_OTHER_CORE OCR.OTHER.L3_HIT.HITM_OTHER_CORE", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.OTHER.L3_HIT.HITM_OTHER_CORE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x10003C8000", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT.HIT_OTHER_CORE_FWD OCR.OTHER.L3_HIT.HIT_OTHER_CORE_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.OTHER.L3_HIT.HIT_OTHER_CORE_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x8003C8000", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.OTHER.L3_HIT.HIT_OTHER_CORE_NO_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.OTHER.L3_HIT.HIT_OTHER_CORE_NO_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x4003C8000", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT.NO_SNOOP_NEEDED OCR.OTHER.L3_HIT.NO_SNOOP_NEEDED", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.OTHER.L3_HIT.NO_SNOOP_NEEDED", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x1003C8000", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts any other requests", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.OTHER.L3_HIT.SNOOP_HIT_WITH_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x8007C8000", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT.SNOOP_MISS", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.OTHER.L3_HIT.SNOOP_MISS", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x2003C8000", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT.SNOOP_NONE", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.OTHER.L3_HIT.SNOOP_NONE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x803C8000", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_E.ANY_SNOOP", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.OTHER.L3_HIT_E.ANY_SNOOP", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x3F80088000", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_E.HITM_OTHER_CORE", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.OTHER.L3_HIT_E.HITM_OTHER_CORE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x1000088000", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_E.HIT_OTHER_CORE_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.OTHER.L3_HIT_E.HIT_OTHER_CORE_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x800088000", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.OTHER.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x400088000", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_E.NO_SNOOP_NEEDED", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.OTHER.L3_HIT_E.NO_SNOOP_NEEDED", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x100088000", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts any other requests", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.OTHER.L3_HIT_E.SNOOP_MISS", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x200088000", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts any other requests", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.OTHER.L3_HIT_E.SNOOP_NONE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x80088000", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_F.ANY_SNOOP", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.OTHER.L3_HIT_F.ANY_SNOOP", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x3F80208000", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_F.HITM_OTHER_CORE", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.OTHER.L3_HIT_F.HITM_OTHER_CORE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x1000208000", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_F.HIT_OTHER_CORE_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.OTHER.L3_HIT_F.HIT_OTHER_CORE_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x800208000", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.OTHER.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x400208000", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_F.NO_SNOOP_NEEDED", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.OTHER.L3_HIT_F.NO_SNOOP_NEEDED", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x100208000", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts any other requests", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.OTHER.L3_HIT_F.SNOOP_MISS", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x200208000", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts any other requests", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.OTHER.L3_HIT_F.SNOOP_NONE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x80208000", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_M.ANY_SNOOP", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.OTHER.L3_HIT_M.ANY_SNOOP", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x3F80048000", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_M.HITM_OTHER_CORE", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.OTHER.L3_HIT_M.HITM_OTHER_CORE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x1000048000", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_M.HIT_OTHER_CORE_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.OTHER.L3_HIT_M.HIT_OTHER_CORE_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x800048000", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.OTHER.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x400048000", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_M.NO_SNOOP_NEEDED", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.OTHER.L3_HIT_M.NO_SNOOP_NEEDED", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x100048000", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts any other requests", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.OTHER.L3_HIT_M.SNOOP_MISS", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x200048000", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts any other requests", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.OTHER.L3_HIT_M.SNOOP_NONE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x80048000", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_S.ANY_SNOOP", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.OTHER.L3_HIT_S.ANY_SNOOP", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x3F80108000", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_S.HITM_OTHER_CORE", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.OTHER.L3_HIT_S.HITM_OTHER_CORE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x1000108000", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_S.HIT_OTHER_CORE_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.OTHER.L3_HIT_S.HIT_OTHER_CORE_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x800108000", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.OTHER.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x400108000", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_S.NO_SNOOP_NEEDED", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.OTHER.L3_HIT_S.NO_SNOOP_NEEDED", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x100108000", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts any other requests", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.OTHER.L3_HIT_S.SNOOP_MISS", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x200108000", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts any other requests", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.OTHER.L3_HIT_S.SNOOP_NONE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x80108000", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts any other requests OCR.OTHER.PMM_HIT_LOCAL_PMM.ANY_SNOOP", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.OTHER.PMM_HIT_LOCAL_PMM.ANY_SNOOP", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x3F80408000", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts any other requests OCR.OTHER.PMM_HIT_LOCAL_PMM.SNOOP_NONE", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.OTHER.PMM_HIT_LOCAL_PMM.SNOOP_NONE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x80408000", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts any other requests OCR.OTHER.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.OTHER.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x100408000", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts any other requests OCR.OTHER.SUPPLIER_NONE.ANY_SNOOP", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.OTHER.SUPPLIER_NONE.ANY_SNOOP", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x3F80028000", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts any other requests OCR.OTHER.SUPPLIER_NONE.HITM_OTHER_CORE", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.OTHER.SUPPLIER_NONE.HITM_OTHER_CORE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x1000028000", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts any other requests OCR.OTHER.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.OTHER.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x800028000", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts any other requests OCR.OTHER.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.OTHER.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x400028000", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts any other requests OCR.OTHER.SUPPLIER_NONE.NO_SNOOP_NEEDED", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.OTHER.SUPPLIER_NONE.NO_SNOOP_NEEDED", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x100028000", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts any other requests", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.OTHER.SUPPLIER_NONE.SNOOP_MISS", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x200028000", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts any other requests", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.OTHER.SUPPLIER_NONE.SNOOP_NONE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x80028000", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests have any response type.", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L1D_AND_SW.ANY_RESPONSE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x10400", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT.ANY_SNOOP OCR.PF_L1D_AND_SW.L3_HIT.ANY_SNOOP", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L1D_AND_SW.L3_HIT.ANY_SNOOP", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x3F803C0400", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT.HITM_OTHER_CORE OCR.PF_L1D_AND_SW.L3_HIT.HITM_OTHER_CORE", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L1D_AND_SW.L3_HIT.HITM_OTHER_CORE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x10003C0400", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT.HIT_OTHER_CORE_FWD OCR.PF_L1D_AND_SW.L3_HIT.HIT_OTHER_CORE_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L1D_AND_SW.L3_HIT.HIT_OTHER_CORE_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x8003C0400", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.PF_L1D_AND_SW.L3_HIT.HIT_OTHER_CORE_NO_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L1D_AND_SW.L3_HIT.HIT_OTHER_CORE_NO_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x4003C0400", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT.NO_SNOOP_NEEDED OCR.PF_L1D_AND_SW.L3_HIT.NO_SNOOP_NEEDED", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L1D_AND_SW.L3_HIT.NO_SNOOP_NEEDED", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x1003C0400", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L1D_AND_SW.L3_HIT.SNOOP_HIT_WITH_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x8007C0400", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT.SNOOP_MISS", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L1D_AND_SW.L3_HIT.SNOOP_MISS", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x2003C0400", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT.SNOOP_NONE", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L1D_AND_SW.L3_HIT.SNOOP_NONE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x803C0400", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_E.ANY_SNOOP", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_E.ANY_SNOOP", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x3F80080400", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_E.HITM_OTHER_CORE", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_E.HITM_OTHER_CORE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x1000080400", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_E.HIT_OTHER_CORE_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_E.HIT_OTHER_CORE_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x800080400", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x400080400", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_E.NO_SNOOP_NEEDED", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_E.NO_SNOOP_NEEDED", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x100080400", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_E.SNOOP_MISS", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x200080400", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_E.SNOOP_NONE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x80080400", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_F.ANY_SNOOP", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_F.ANY_SNOOP", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x3F80200400", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_F.HITM_OTHER_CORE", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_F.HITM_OTHER_CORE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x1000200400", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_F.HIT_OTHER_CORE_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_F.HIT_OTHER_CORE_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x800200400", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x400200400", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_F.NO_SNOOP_NEEDED", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_F.NO_SNOOP_NEEDED", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x100200400", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_F.SNOOP_MISS", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x200200400", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_F.SNOOP_NONE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x80200400", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_M.ANY_SNOOP", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_M.ANY_SNOOP", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x3F80040400", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_M.HITM_OTHER_CORE", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_M.HITM_OTHER_CORE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x1000040400", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_M.HIT_OTHER_CORE_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_M.HIT_OTHER_CORE_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x800040400", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x400040400", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_M.NO_SNOOP_NEEDED", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_M.NO_SNOOP_NEEDED", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x100040400", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_M.SNOOP_MISS", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x200040400", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_M.SNOOP_NONE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x80040400", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_S.ANY_SNOOP", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_S.ANY_SNOOP", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x3F80100400", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_S.HITM_OTHER_CORE", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_S.HITM_OTHER_CORE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x1000100400", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_S.HIT_OTHER_CORE_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_S.HIT_OTHER_CORE_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x800100400", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x400100400", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_S.NO_SNOOP_NEEDED", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_S.NO_SNOOP_NEEDED", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x100100400", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_S.SNOOP_MISS", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x200100400", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_S.SNOOP_NONE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x80100400", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.PMM_HIT_LOCAL_PMM.ANY_SNOOP", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L1D_AND_SW.PMM_HIT_LOCAL_PMM.ANY_SNOOP", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x3F80400400", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.PMM_HIT_LOCAL_PMM.SNOOP_NONE", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L1D_AND_SW.PMM_HIT_LOCAL_PMM.SNOOP_NONE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x80400400", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L1D_AND_SW.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x100400400", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.SUPPLIER_NONE.ANY_SNOOP", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L1D_AND_SW.SUPPLIER_NONE.ANY_SNOOP", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x3F80020400", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.SUPPLIER_NONE.HITM_OTHER_CORE", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L1D_AND_SW.SUPPLIER_NONE.HITM_OTHER_CORE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x1000020400", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L1D_AND_SW.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x800020400", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L1D_AND_SW.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x400020400", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.SUPPLIER_NONE.NO_SNOOP_NEEDED", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L1D_AND_SW.SUPPLIER_NONE.NO_SNOOP_NEEDED", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x100020400", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L1D_AND_SW.SUPPLIER_NONE.SNOOP_MISS", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x200020400", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L1D_AND_SW.SUPPLIER_NONE.SNOOP_NONE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x80020400", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts prefetch (that bring data to L2) data reads have any response type.", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L2_DATA_RD.ANY_RESPONSE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x10010", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT.ANY_SNOOP OCR.PF_L2_DATA_RD.L3_HIT.ANY_SNOOP", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L2_DATA_RD.L3_HIT.ANY_SNOOP", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x3F803C0010", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT.HITM_OTHER_CORE OCR.PF_L2_DATA_RD.L3_HIT.HITM_OTHER_CORE", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L2_DATA_RD.L3_HIT.HITM_OTHER_CORE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x10003C0010", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD OCR.PF_L2_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L2_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x8003C0010", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.PF_L2_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L2_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x4003C0010", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT.NO_SNOOP_NEEDED OCR.PF_L2_DATA_RD.L3_HIT.NO_SNOOP_NEEDED", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L2_DATA_RD.L3_HIT.NO_SNOOP_NEEDED", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x1003C0010", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts prefetch (that bring data to L2) data reads", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L2_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x8007C0010", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT.SNOOP_MISS", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L2_DATA_RD.L3_HIT.SNOOP_MISS", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x2003C0010", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT.SNOOP_NONE", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L2_DATA_RD.L3_HIT.SNOOP_NONE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x803C0010", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_E.ANY_SNOOP", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_E.ANY_SNOOP", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x3F80080010", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_E.HITM_OTHER_CORE", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_E.HITM_OTHER_CORE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x1000080010", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x800080010", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x400080010", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x100080010", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts prefetch (that bring data to L2) data reads", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_E.SNOOP_MISS", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x200080010", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts prefetch (that bring data to L2) data reads", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_E.SNOOP_NONE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x80080010", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_F.ANY_SNOOP", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_F.ANY_SNOOP", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x3F80200010", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_F.HITM_OTHER_CORE", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_F.HITM_OTHER_CORE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x1000200010", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x800200010", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x400200010", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x100200010", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts prefetch (that bring data to L2) data reads", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_F.SNOOP_MISS", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x200200010", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts prefetch (that bring data to L2) data reads", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_F.SNOOP_NONE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x80200010", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_M.ANY_SNOOP", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_M.ANY_SNOOP", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x3F80040010", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_M.HITM_OTHER_CORE", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_M.HITM_OTHER_CORE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x1000040010", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x800040010", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x400040010", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x100040010", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts prefetch (that bring data to L2) data reads", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_M.SNOOP_MISS", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x200040010", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts prefetch (that bring data to L2) data reads", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_M.SNOOP_NONE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x80040010", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_S.ANY_SNOOP", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_S.ANY_SNOOP", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x3F80100010", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_S.HITM_OTHER_CORE", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_S.HITM_OTHER_CORE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x1000100010", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x800100010", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x400100010", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x100100010", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts prefetch (that bring data to L2) data reads", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_S.SNOOP_MISS", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x200100010", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts prefetch (that bring data to L2) data reads", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_S.SNOOP_NONE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x80100010", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L2_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x3F80400010", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L2_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x80400010", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L2_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x100400010", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.SUPPLIER_NONE.ANY_SNOOP", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L2_DATA_RD.SUPPLIER_NONE.ANY_SNOOP", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x3F80020010", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L2_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x1000020010", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L2_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x800020010", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L2_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x400020010", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L2_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x100020010", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts prefetch (that bring data to L2) data reads", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L2_DATA_RD.SUPPLIER_NONE.SNOOP_MISS", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x200020010", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts prefetch (that bring data to L2) data reads", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L2_DATA_RD.SUPPLIER_NONE.SNOOP_NONE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x80020010", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs have any response type.", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L2_RFO.ANY_RESPONSE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x10020", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT.ANY_SNOOP OCR.PF_L2_RFO.L3_HIT.ANY_SNOOP", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L2_RFO.L3_HIT.ANY_SNOOP", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x3F803C0020", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT.HITM_OTHER_CORE OCR.PF_L2_RFO.L3_HIT.HITM_OTHER_CORE", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L2_RFO.L3_HIT.HITM_OTHER_CORE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x10003C0020", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT.HIT_OTHER_CORE_FWD OCR.PF_L2_RFO.L3_HIT.HIT_OTHER_CORE_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L2_RFO.L3_HIT.HIT_OTHER_CORE_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x8003C0020", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.PF_L2_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L2_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x4003C0020", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT.NO_SNOOP_NEEDED OCR.PF_L2_RFO.L3_HIT.NO_SNOOP_NEEDED", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L2_RFO.L3_HIT.NO_SNOOP_NEEDED", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x1003C0020", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L2_RFO.L3_HIT.SNOOP_HIT_WITH_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x8007C0020", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT.SNOOP_MISS", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L2_RFO.L3_HIT.SNOOP_MISS", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x2003C0020", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT.SNOOP_NONE", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L2_RFO.L3_HIT.SNOOP_NONE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x803C0020", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_E.ANY_SNOOP", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L2_RFO.L3_HIT_E.ANY_SNOOP", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x3F80080020", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_E.HITM_OTHER_CORE", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L2_RFO.L3_HIT_E.HITM_OTHER_CORE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x1000080020", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L2_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x800080020", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L2_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x400080020", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_E.NO_SNOOP_NEEDED", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L2_RFO.L3_HIT_E.NO_SNOOP_NEEDED", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x100080020", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L2_RFO.L3_HIT_E.SNOOP_MISS", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x200080020", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L2_RFO.L3_HIT_E.SNOOP_NONE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x80080020", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_F.ANY_SNOOP", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L2_RFO.L3_HIT_F.ANY_SNOOP", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x3F80200020", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_F.HITM_OTHER_CORE", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L2_RFO.L3_HIT_F.HITM_OTHER_CORE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x1000200020", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L2_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x800200020", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L2_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x400200020", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_F.NO_SNOOP_NEEDED", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L2_RFO.L3_HIT_F.NO_SNOOP_NEEDED", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x100200020", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L2_RFO.L3_HIT_F.SNOOP_MISS", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x200200020", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L2_RFO.L3_HIT_F.SNOOP_NONE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x80200020", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_M.ANY_SNOOP", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L2_RFO.L3_HIT_M.ANY_SNOOP", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x3F80040020", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_M.HITM_OTHER_CORE", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L2_RFO.L3_HIT_M.HITM_OTHER_CORE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x1000040020", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L2_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x800040020", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L2_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x400040020", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_M.NO_SNOOP_NEEDED", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L2_RFO.L3_HIT_M.NO_SNOOP_NEEDED", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x100040020", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L2_RFO.L3_HIT_M.SNOOP_MISS", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x200040020", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L2_RFO.L3_HIT_M.SNOOP_NONE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x80040020", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_S.ANY_SNOOP", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L2_RFO.L3_HIT_S.ANY_SNOOP", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x3F80100020", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_S.HITM_OTHER_CORE", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L2_RFO.L3_HIT_S.HITM_OTHER_CORE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x1000100020", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L2_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x800100020", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L2_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x400100020", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_S.NO_SNOOP_NEEDED", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L2_RFO.L3_HIT_S.NO_SNOOP_NEEDED", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x100100020", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L2_RFO.L3_HIT_S.SNOOP_MISS", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x200100020", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L2_RFO.L3_HIT_S.SNOOP_NONE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x80100020", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L2_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x3F80400020", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L2_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x80400020", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L2_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x100400020", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.SUPPLIER_NONE.ANY_SNOOP", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L2_RFO.SUPPLIER_NONE.ANY_SNOOP", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x3F80020020", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.SUPPLIER_NONE.HITM_OTHER_CORE", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L2_RFO.SUPPLIER_NONE.HITM_OTHER_CORE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x1000020020", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L2_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x800020020", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L2_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x400020020", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L2_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x100020020", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L2_RFO.SUPPLIER_NONE.SNOOP_MISS", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x200020020", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L2_RFO.SUPPLIER_NONE.SNOOP_NONE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x80020020", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads have any response type.", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L3_DATA_RD.ANY_RESPONSE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x10080", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT.ANY_SNOOP OCR.PF_L3_DATA_RD.L3_HIT.ANY_SNOOP", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L3_DATA_RD.L3_HIT.ANY_SNOOP", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x3F803C0080", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT.HITM_OTHER_CORE OCR.PF_L3_DATA_RD.L3_HIT.HITM_OTHER_CORE", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L3_DATA_RD.L3_HIT.HITM_OTHER_CORE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x10003C0080", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD OCR.PF_L3_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L3_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x8003C0080", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.PF_L3_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L3_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x4003C0080", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT.NO_SNOOP_NEEDED OCR.PF_L3_DATA_RD.L3_HIT.NO_SNOOP_NEEDED", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L3_DATA_RD.L3_HIT.NO_SNOOP_NEEDED", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x1003C0080", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L3_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x8007C0080", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT.SNOOP_MISS", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L3_DATA_RD.L3_HIT.SNOOP_MISS", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x2003C0080", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT.SNOOP_NONE", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L3_DATA_RD.L3_HIT.SNOOP_NONE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x803C0080", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_E.ANY_SNOOP", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_E.ANY_SNOOP", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x3F80080080", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_E.HITM_OTHER_CORE", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_E.HITM_OTHER_CORE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x1000080080", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x800080080", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x400080080", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x100080080", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_E.SNOOP_MISS", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x200080080", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_E.SNOOP_NONE", > + "EventName": "OCR.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_MISS", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x80080080", > + "MSRValue": "0x200020001", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_F.ANY_SNOOP", > + "BriefDescription": "Counts demand data reads", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_F.ANY_SNOOP", > + "EventName": "OCR.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_NONE", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x3F80200080", > + "MSRValue": "0x80020001", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_F.HITM_OTHER_CORE", > + "BriefDescription": "Counts all demand data writes (RFOs) have any response type.", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_F.HITM_OTHER_CORE", > + "EventName": "OCR.DEMAND_RFO.ANY_RESPONSE", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x1000200080", > + "MSRValue": "0x10002", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD", > + "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD", > + "EventName": "OCR.DEMAND_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x800200080", > + "MSRValue": "0x3F80400002", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", > + "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", > + "EventName": "OCR.DEMAND_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x400200080", > + "MSRValue": "0x80400002", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED", > + "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED", > + "EventName": "OCR.DEMAND_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x100200080", > + "MSRValue": "0x100400002", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", > + "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.SUPPLIER_NONE.ANY_SNOOP", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_F.SNOOP_MISS", > + "EventName": "OCR.DEMAND_RFO.SUPPLIER_NONE.ANY_SNOOP", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x200200080", > + "MSRValue": "0x3F80020002", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", > + "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.SUPPLIER_NONE.HITM_OTHER_CORE", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_F.SNOOP_NONE", > + "EventName": "OCR.DEMAND_RFO.SUPPLIER_NONE.HITM_OTHER_CORE", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x80200080", > + "MSRValue": "0x1000020002", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_M.ANY_SNOOP", > + "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_M.ANY_SNOOP", > + "EventName": "OCR.DEMAND_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x3F80040080", > + "MSRValue": "0x800020002", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_M.HITM_OTHER_CORE", > + "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_M.HITM_OTHER_CORE", > + "EventName": "OCR.DEMAND_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x1000040080", > + "MSRValue": "0x400020002", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD", > + "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD", > + "EventName": "OCR.DEMAND_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x800040080", > + "MSRValue": "0x100020002", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", > + "BriefDescription": "Counts all demand data writes (RFOs)", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", > + "EventName": "OCR.DEMAND_RFO.SUPPLIER_NONE.SNOOP_MISS", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x400040080", > + "MSRValue": "0x200020002", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED", > + "BriefDescription": "Counts all demand data writes (RFOs)", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED", > + "EventName": "OCR.DEMAND_RFO.SUPPLIER_NONE.SNOOP_NONE", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x100040080", > + "MSRValue": "0x80020002", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", > + "BriefDescription": "Counts any other requests have any response type.", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_M.SNOOP_MISS", > + "EventName": "OCR.OTHER.ANY_RESPONSE", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x200040080", > + "MSRValue": "0x18000", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", > + "BriefDescription": "Counts any other requests OCR.OTHER.PMM_HIT_LOCAL_PMM.ANY_SNOOP", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_M.SNOOP_NONE", > + "EventName": "OCR.OTHER.PMM_HIT_LOCAL_PMM.ANY_SNOOP", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x80040080", > + "MSRValue": "0x3F80408000", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_S.ANY_SNOOP", > + "BriefDescription": "Counts any other requests OCR.OTHER.PMM_HIT_LOCAL_PMM.SNOOP_NONE", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_S.ANY_SNOOP", > + "EventName": "OCR.OTHER.PMM_HIT_LOCAL_PMM.SNOOP_NONE", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x3F80100080", > + "MSRValue": "0x80408000", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_S.HITM_OTHER_CORE", > + "BriefDescription": "Counts any other requests OCR.OTHER.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_S.HITM_OTHER_CORE", > + "EventName": "OCR.OTHER.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x1000100080", > + "MSRValue": "0x100408000", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD", > + "BriefDescription": "Counts any other requests OCR.OTHER.SUPPLIER_NONE.ANY_SNOOP", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD", > + "EventName": "OCR.OTHER.SUPPLIER_NONE.ANY_SNOOP", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x800100080", > + "MSRValue": "0x3F80028000", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", > + "BriefDescription": "Counts any other requests OCR.OTHER.SUPPLIER_NONE.HITM_OTHER_CORE", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", > + "EventName": "OCR.OTHER.SUPPLIER_NONE.HITM_OTHER_CORE", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x400100080", > + "MSRValue": "0x1000028000", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED", > + "BriefDescription": "Counts any other requests OCR.OTHER.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED", > + "EventName": "OCR.OTHER.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x100100080", > + "MSRValue": "0x800028000", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", > + "BriefDescription": "Counts any other requests OCR.OTHER.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_S.SNOOP_MISS", > + "EventName": "OCR.OTHER.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x200100080", > + "MSRValue": "0x400028000", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", > + "BriefDescription": "Counts any other requests OCR.OTHER.SUPPLIER_NONE.NO_SNOOP_NEEDED", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_S.SNOOP_NONE", > + "EventName": "OCR.OTHER.SUPPLIER_NONE.NO_SNOOP_NEEDED", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x80100080", > + "MSRValue": "0x100028000", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP", > + "BriefDescription": "Counts any other requests", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L3_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP", > + "EventName": "OCR.OTHER.SUPPLIER_NONE.SNOOP_MISS", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x3F80400080", > + "MSRValue": "0x200028000", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE", > + "BriefDescription": "Counts any other requests", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L3_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE", > + "EventName": "OCR.OTHER.SUPPLIER_NONE.SNOOP_NONE", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x80400080", > + "MSRValue": "0x80028000", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", > + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests have any response type.", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L3_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", > + "EventName": "OCR.PF_L1D_AND_SW.ANY_RESPONSE", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x100400080", > + "MSRValue": "0x10400", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.SUPPLIER_NONE.ANY_SNOOP", > + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.PMM_HIT_LOCAL_PMM.ANY_SNOOP", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L3_DATA_RD.SUPPLIER_NONE.ANY_SNOOP", > + "EventName": "OCR.PF_L1D_AND_SW.PMM_HIT_LOCAL_PMM.ANY_SNOOP", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x3F80020080", > + "MSRValue": "0x3F80400400", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE", > + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.PMM_HIT_LOCAL_PMM.SNOOP_NONE", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L3_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE", > + "EventName": "OCR.PF_L1D_AND_SW.PMM_HIT_LOCAL_PMM.SNOOP_NONE", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x1000020080", > + "MSRValue": "0x80400400", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", > + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L3_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", > + "EventName": "OCR.PF_L1D_AND_SW.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x800020080", > + "MSRValue": "0x100400400", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", > + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.SUPPLIER_NONE.ANY_SNOOP", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L3_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", > + "EventName": "OCR.PF_L1D_AND_SW.SUPPLIER_NONE.ANY_SNOOP", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x400020080", > + "MSRValue": "0x3F80020400", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED", > + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.SUPPLIER_NONE.HITM_OTHER_CORE", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L3_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED", > + "EventName": "OCR.PF_L1D_AND_SW.SUPPLIER_NONE.HITM_OTHER_CORE", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x100020080", > + "MSRValue": "0x1000020400", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", > + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L3_DATA_RD.SUPPLIER_NONE.SNOOP_MISS", > + "EventName": "OCR.PF_L1D_AND_SW.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x200020080", > + "MSRValue": "0x800020400", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", > + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L3_DATA_RD.SUPPLIER_NONE.SNOOP_NONE", > + "EventName": "OCR.PF_L1D_AND_SW.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x80020080", > + "MSRValue": "0x400020400", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs have any response type.", > + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.SUPPLIER_NONE.NO_SNOOP_NEEDED", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L3_RFO.ANY_RESPONSE", > + "EventName": "OCR.PF_L1D_AND_SW.SUPPLIER_NONE.NO_SNOOP_NEEDED", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x10100", > + "MSRValue": "0x100020400", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT.ANY_SNOOP OCR.PF_L3_RFO.L3_HIT.ANY_SNOOP", > + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L3_RFO.L3_HIT.ANY_SNOOP", > + "EventName": "OCR.PF_L1D_AND_SW.SUPPLIER_NONE.SNOOP_MISS", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x3F803C0100", > + "MSRValue": "0x200020400", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT.HITM_OTHER_CORE OCR.PF_L3_RFO.L3_HIT.HITM_OTHER_CORE", > + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L3_RFO.L3_HIT.HITM_OTHER_CORE", > + "EventName": "OCR.PF_L1D_AND_SW.SUPPLIER_NONE.SNOOP_NONE", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x10003C0100", > + "MSRValue": "0x80020400", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT.HIT_OTHER_CORE_FWD OCR.PF_L3_RFO.L3_HIT.HIT_OTHER_CORE_FWD", > + "BriefDescription": "Counts prefetch (that bring data to L2) data reads have any response type.", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L3_RFO.L3_HIT.HIT_OTHER_CORE_FWD", > + "EventName": "OCR.PF_L2_DATA_RD.ANY_RESPONSE", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x8003C0100", > + "MSRValue": "0x10010", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.PF_L3_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD", > + "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L3_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD", > + "EventName": "OCR.PF_L2_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x4003C0100", > + "MSRValue": "0x3F80400010", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT.NO_SNOOP_NEEDED OCR.PF_L3_RFO.L3_HIT.NO_SNOOP_NEEDED", > + "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L3_RFO.L3_HIT.NO_SNOOP_NEEDED", > + "EventName": "OCR.PF_L2_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x1003C0100", > + "MSRValue": "0x80400010", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", > + "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L3_RFO.L3_HIT.SNOOP_HIT_WITH_FWD", > + "EventName": "OCR.PF_L2_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x8007C0100", > + "MSRValue": "0x100400010", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT.SNOOP_MISS", > + "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.SUPPLIER_NONE.ANY_SNOOP", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L3_RFO.L3_HIT.SNOOP_MISS", > + "EventName": "OCR.PF_L2_DATA_RD.SUPPLIER_NONE.ANY_SNOOP", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x2003C0100", > + "MSRValue": "0x3F80020010", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT.SNOOP_NONE", > + "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L3_RFO.L3_HIT.SNOOP_NONE", > + "EventName": "OCR.PF_L2_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x803C0100", > + "MSRValue": "0x1000020010", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_E.ANY_SNOOP", > + "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L3_RFO.L3_HIT_E.ANY_SNOOP", > + "EventName": "OCR.PF_L2_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x3F80080100", > + "MSRValue": "0x800020010", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_E.HITM_OTHER_CORE", > + "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L3_RFO.L3_HIT_E.HITM_OTHER_CORE", > + "EventName": "OCR.PF_L2_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x1000080100", > + "MSRValue": "0x400020010", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD", > + "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L3_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD", > + "EventName": "OCR.PF_L2_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x800080100", > + "MSRValue": "0x100020010", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", > + "BriefDescription": "Counts prefetch (that bring data to L2) data reads", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L3_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", > + "EventName": "OCR.PF_L2_DATA_RD.SUPPLIER_NONE.SNOOP_MISS", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x400080100", > + "MSRValue": "0x200020010", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_E.NO_SNOOP_NEEDED", > + "BriefDescription": "Counts prefetch (that bring data to L2) data reads", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L3_RFO.L3_HIT_E.NO_SNOOP_NEEDED", > + "EventName": "OCR.PF_L2_DATA_RD.SUPPLIER_NONE.SNOOP_NONE", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x100080100", > + "MSRValue": "0x80020010", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", > + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs have any response type.", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L3_RFO.L3_HIT_E.SNOOP_MISS", > + "EventName": "OCR.PF_L2_RFO.ANY_RESPONSE", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x200080100", > + "MSRValue": "0x10020", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", > + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L3_RFO.L3_HIT_E.SNOOP_NONE", > + "EventName": "OCR.PF_L2_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x80080100", > + "MSRValue": "0x3F80400020", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_F.ANY_SNOOP", > + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L3_RFO.L3_HIT_F.ANY_SNOOP", > + "EventName": "OCR.PF_L2_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x3F80200100", > + "MSRValue": "0x80400020", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_F.HITM_OTHER_CORE", > + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L3_RFO.L3_HIT_F.HITM_OTHER_CORE", > + "EventName": "OCR.PF_L2_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x1000200100", > + "MSRValue": "0x100400020", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD", > + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.SUPPLIER_NONE.ANY_SNOOP", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L3_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD", > + "EventName": "OCR.PF_L2_RFO.SUPPLIER_NONE.ANY_SNOOP", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x800200100", > + "MSRValue": "0x3F80020020", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", > + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.SUPPLIER_NONE.HITM_OTHER_CORE", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L3_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", > + "EventName": "OCR.PF_L2_RFO.SUPPLIER_NONE.HITM_OTHER_CORE", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x400200100", > + "MSRValue": "0x1000020020", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_F.NO_SNOOP_NEEDED", > + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L3_RFO.L3_HIT_F.NO_SNOOP_NEEDED", > + "EventName": "OCR.PF_L2_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x100200100", > + "MSRValue": "0x800020020", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", > + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L3_RFO.L3_HIT_F.SNOOP_MISS", > + "EventName": "OCR.PF_L2_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x200200100", > + "MSRValue": "0x400020020", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", > + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L3_RFO.L3_HIT_F.SNOOP_NONE", > + "EventName": "OCR.PF_L2_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x80200100", > + "MSRValue": "0x100020020", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_M.ANY_SNOOP", > + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L3_RFO.L3_HIT_M.ANY_SNOOP", > + "EventName": "OCR.PF_L2_RFO.SUPPLIER_NONE.SNOOP_MISS", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x3F80040100", > + "MSRValue": "0x200020020", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_M.HITM_OTHER_CORE", > + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L3_RFO.L3_HIT_M.HITM_OTHER_CORE", > + "EventName": "OCR.PF_L2_RFO.SUPPLIER_NONE.SNOOP_NONE", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x1000040100", > + "MSRValue": "0x80020020", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD", > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads have any response type.", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L3_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD", > + "EventName": "OCR.PF_L3_DATA_RD.ANY_RESPONSE", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x800040100", > + "MSRValue": "0x10080", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L3_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", > + "EventName": "OCR.PF_L3_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x400040100", > + "MSRValue": "0x3F80400080", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_M.NO_SNOOP_NEEDED", > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L3_RFO.L3_HIT_M.NO_SNOOP_NEEDED", > + "EventName": "OCR.PF_L3_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x100040100", > + "MSRValue": "0x80400080", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L3_RFO.L3_HIT_M.SNOOP_MISS", > + "EventName": "OCR.PF_L3_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x200040100", > + "MSRValue": "0x100400080", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.SUPPLIER_NONE.ANY_SNOOP", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L3_RFO.L3_HIT_M.SNOOP_NONE", > + "EventName": "OCR.PF_L3_DATA_RD.SUPPLIER_NONE.ANY_SNOOP", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x80040100", > + "MSRValue": "0x3F80020080", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_S.ANY_SNOOP", > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L3_RFO.L3_HIT_S.ANY_SNOOP", > + "EventName": "OCR.PF_L3_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x3F80100100", > + "MSRValue": "0x1000020080", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_S.HITM_OTHER_CORE", > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L3_RFO.L3_HIT_S.HITM_OTHER_CORE", > + "EventName": "OCR.PF_L3_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x1000100100", > + "MSRValue": "0x800020080", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD", > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L3_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD", > + "EventName": "OCR.PF_L3_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x800100100", > + "MSRValue": "0x400020080", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L3_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", > + "EventName": "OCR.PF_L3_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x400100100", > + "MSRValue": "0x100020080", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_S.NO_SNOOP_NEEDED", > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L3_RFO.L3_HIT_S.NO_SNOOP_NEEDED", > + "EventName": "OCR.PF_L3_DATA_RD.SUPPLIER_NONE.SNOOP_MISS", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x100100100", > + "MSRValue": "0x200020080", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L3_RFO.L3_HIT_S.SNOOP_MISS", > + "EventName": "OCR.PF_L3_DATA_RD.SUPPLIER_NONE.SNOOP_NONE", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x200100100", > + "MSRValue": "0x80020080", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs have any response type.", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L3_RFO.L3_HIT_S.SNOOP_NONE", > + "EventName": "OCR.PF_L3_RFO.ANY_RESPONSE", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x80100100", > + "MSRValue": "0x10100", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > @@ -8622,41 +2070,5 @@ > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > - }, > - { > - "BriefDescription": "Number of PREFETCHNTA instructions executed.", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3,4,5,6,7", > - "EventCode": "0x32", > - "EventName": "SW_PREFETCH_ACCESS.NTA", > - "SampleAfterValue": "2000003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Number of PREFETCHW instructions executed.", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3,4,5,6,7", > - "EventCode": "0x32", > - "EventName": "SW_PREFETCH_ACCESS.PREFETCHW", > - "SampleAfterValue": "2000003", > - "UMask": "0x8" > - }, > - { > - "BriefDescription": "Number of PREFETCHT0 instructions executed.", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3,4,5,6,7", > - "EventCode": "0x32", > - "EventName": "SW_PREFETCH_ACCESS.T0", > - "SampleAfterValue": "2000003", > - "UMask": "0x2" > - }, > - { > - "BriefDescription": "Number of PREFETCHT1 or PREFETCHT2 instructions executed.", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3,4,5,6,7", > - "EventCode": "0x32", > - "EventName": "SW_PREFETCH_ACCESS.T1_T2", > - "SampleAfterValue": "2000003", > - "UMask": "0x4" > } > ] > \ No newline at end of file -- Zhengjun Xing