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[2620:137:e000::1:18]) by mx.google.com with ESMTPS id fs12-20020a17090af28c00b001bd319449c9si493356pjb.91.2022.03.21.15.24.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 21 Mar 2022 15:24:09 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:18 as permitted sender) client-ip=2620:137:e000::1:18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id E14A8389F22; Mon, 21 Mar 2022 14:39:54 -0700 (PDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1351135AbiCUQbT (ORCPT + 99 others); Mon, 21 Mar 2022 12:31:19 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58022 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1351119AbiCUQbR (ORCPT ); Mon, 21 Mar 2022 12:31:17 -0400 Received: from 189.cn (ptr.189.cn [183.61.185.104]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id C161F506F3; Mon, 21 Mar 2022 09:29:49 -0700 (PDT) HMM_SOURCE_IP: 10.64.8.43:55736.678671471 HMM_ATTACHE_NUM: 0000 HMM_SOURCE_TYPE: SMTP Received: from clientip-114.242.206.180 (unknown [10.64.8.43]) by 189.cn (HERMES) with SMTP id 0263C100248; Tue, 22 Mar 2022 00:29:45 +0800 (CST) Received: from ([114.242.206.180]) by gateway-151646-dep-b7fbf7d79-vjdjk with ESMTP id d76ae6ec35524f06aa4b2f3b376ff736 for mripard@kernel.org; Tue, 22 Mar 2022 00:29:47 CST X-Transaction-ID: d76ae6ec35524f06aa4b2f3b376ff736 X-Real-From: 15330273260@189.cn X-Receive-IP: 114.242.206.180 X-MEDUSA-Status: 0 Sender: 15330273260@189.cn From: Sui Jingfeng <15330273260@189.cn> To: Maxime Ripard , Thomas Zimmermann , Roland Scheidegger , Zack Rusin , Christian Gmeiner , David Airlie , Daniel Vetter , Rob Herring , Thomas Bogendoerfer , Dan Carpenter , Krzysztof Kozlowski , Andrey Zhizhikin , Sam Ravnborg , "David S . Miller" , Jiaxun Yang , Lucas Stach , Maarten Lankhorst , Ilia Mirkin , Qing Zhang , suijingfeng Cc: linux-mips@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org Subject: [PATCH v11 2/7] MIPS: Loongson64: dts: introduce ls3A4000 evaluation board Date: Tue, 22 Mar 2022 00:29:11 +0800 Message-Id: <20220321162916.1116541-3-15330273260@189.cn> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220321162916.1116541-1-15330273260@189.cn> References: <20220321162916.1116541-1-15330273260@189.cn> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-1.6 required=5.0 tests=BAYES_00, FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM,FROM_LOCAL_DIGITS, FROM_LOCAL_HEX,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, RDNS_NONE,SPF_HELO_NONE,SPOOFED_FREEMAIL_NO_RDNS,T_SCC_BODY_TEXT_LINE autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: suijingfeng The board name is LS3A4000_7A1000_EVB_BOARD_V1.4, it consist of 1.8Ghz mips64r5 4-core CPU and LS7A1000 bridge chip. It has PCIe GEN2 x8 slot, therefore can play with discrete graphics card. While the integrated display copntroller is equipped with a VGA output and a DVI output, the VGA is connect to the DVO0 output port of the display controller, the DVI is connected to DVO1 output port of the display controller. +------+ +-----------------------------------+ | DDR4 | | +-------------------+ | +------+ | | PCIe Root complex | LS7A1000 | || MC0 | +--++---------++----+ | +----------+ HT 3.0 | || || | | LS3A4000 |<-------->| +---++---+ +--++--+ +---------+ +------+ | CPU |<-------->| | GC1000 | | LSDC |<-->| DDR3 MC |<->| VRAM | +----------+ | +--------+ +-+--+-+ +---------+ +------+ || MC1 +---------------|--|----------------+ +------+ | | | DDR4 | +-------+ DVO0 | | DVO1 +------+ +------+ VGA <--|ADV7125|<--------+ +-------->|TFP410|--> DVI/HDMI +-------+ +------+ Signed-off-by: suijingfeng Signed-off-by: Sui Jingfeng <15330273260@189.cn> --- .../boot/dts/loongson/ls3a4000_7a1000_evb.dts | 136 ++++++++++++++++++ 1 file changed, 136 insertions(+) create mode 100644 arch/mips/boot/dts/loongson/ls3a4000_7a1000_evb.dts diff --git a/arch/mips/boot/dts/loongson/ls3a4000_7a1000_evb.dts b/arch/mips/boot/dts/loongson/ls3a4000_7a1000_evb.dts new file mode 100644 index 000000000000..f467eddccdac --- /dev/null +++ b/arch/mips/boot/dts/loongson/ls3a4000_7a1000_evb.dts @@ -0,0 +1,136 @@ +// SPDX-License-Identifier: GPL-2.0 + +/dts-v1/; + +#include "loongson64g-package.dtsi" +#include "ls7a-pch.dtsi" + +/ { + compatible = "loongson,loongson64g-4core-ls7a"; + model = "LS3A4000_7A1000_EVB_BOARD_V1.4"; + + vga-encoder { + compatible = "adi,adv7123", "dumb-vga-dac"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + adv7123_in: endpoint { + remote-endpoint = <&dc_out_rgb0>; + }; + }; + + port@1 { + reg = <1>; + adv7123_out: endpoint { + remote-endpoint = <&vga_connector_in>; + }; + }; + }; + }; + + vga-connector { + compatible = "vga-connector"; + label = "vga"; + + ddc-i2c-bus = <&i2c6>; + + port { + vga_connector_in: endpoint { + remote-endpoint = <&adv7123_out>; + }; + }; + }; + + tfp410: dvi-encoder { + compatible = "ti,tfp410"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + tfp410_in: endpoint { + pclk-sample = <1>; + bus-width = <24>; + remote-endpoint = <&dc_out_rgb1>; + }; + }; + + port@1 { + reg = <1>; + tfp410_out: endpoint { + remote-endpoint = <&dvi_connector_in>; + }; + }; + }; + }; + + dvi-connector { + compatible = "dvi-connector"; + label = "dvi"; + digital; + + ddc-i2c-bus = <&i2c7>; + + port { + dvi_connector_in: endpoint { + remote-endpoint = <&tfp410_out>; + }; + }; + }; +}; + +&package0 { + htvec: interrupt-controller@efdfb000080 { + compatible = "loongson,htvec-1.0"; + reg = <0xefd 0xfb000080 0x40>; + interrupt-controller; + #interrupt-cells = <1>; + + interrupt-parent = <&liointc>; + interrupts = <24 IRQ_TYPE_LEVEL_HIGH>, + <25 IRQ_TYPE_LEVEL_HIGH>, + <26 IRQ_TYPE_LEVEL_HIGH>, + <27 IRQ_TYPE_LEVEL_HIGH>, + <28 IRQ_TYPE_LEVEL_HIGH>, + <29 IRQ_TYPE_LEVEL_HIGH>, + <30 IRQ_TYPE_LEVEL_HIGH>, + <31 IRQ_TYPE_LEVEL_HIGH>; + }; +}; + +&pch { + msi: msi-controller@2ff00000 { + compatible = "loongson,pch-msi-1.0"; + reg = <0 0x2ff00000 0 0x8>; + interrupt-controller; + msi-controller; + loongson,msi-base-vec = <64>; + loongson,msi-num-vecs = <192>; + interrupt-parent = <&htvec>; + }; +}; + +&lsdc { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + endpoint { + remote-endpoint = <&adv7123_in>; + }; + }; + + port@1 { + endpoint { + remote-endpoint = <&tfp410_in>; + }; + }; + }; +}; -- 2.25.1