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From:   Zhiyuan Dai <daizhiyuan@phytium.com.cn>
To:     catalin.marinas@arm.com, will@kernel.org
Cc:     linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org,
        llvm@lists.linux.dev, Zhiyuan Dai <daizhiyuan@phytium.com.cn>
Subject: [PATCH] arm64: assembler: Fine-tune code to improve code readability
Date:   Mon, 21 Mar 2022 10:54:34 +0800
Message-Id: <1647831274-3555-1-git-send-email-daizhiyuan@phytium.com.cn>
Precedence: bulk

This patch tweaks the code to improve readability.

Defined values are:
 PMUVer == 0b0000 : Performance Monitors Extension not implemented.

Signed-off-by: Zhiyuan Dai <daizhiyuan@phytium.com.cn>
---
 arch/arm64/include/asm/assembler.h | 9 ++++-----
 1 file changed, 4 insertions(+), 5 deletions(-)

diff --git a/arch/arm64/include/asm/assembler.h b/arch/arm64/include/asm/assembler.h
index 6ebdc0f..efd43a1 100644
--- a/arch/arm64/include/asm/assembler.h
+++ b/arch/arm64/include/asm/assembler.h
@@ -489,11 +489,10 @@
  */
 	.macro	reset_pmuserenr_el0, tmpreg
 	mrs	\tmpreg, id_aa64dfr0_el1
-	sbfx	\tmpreg, \tmpreg, #ID_AA64DFR0_PMUVER_SHIFT, #4
-	cmp	\tmpreg, #1			// Skip if no PMU present
-	b.lt	9000f
-	msr	pmuserenr_el0, xzr		// Disable PMU access from EL0
-9000:
+	ubfx	\tmpreg, \tmpreg, #ID_AA64DFR0_PMUVER_SHIFT, #4
+	cbz	\tmpreg, .Lskip_pmu_\@		// Skip if no PMU present
+	msr_s   SYS_PMUSERENR_EL0, xzr	// Disable PMU access from EL0
+.Lskip_pmu_\@:
 	.endm
 
 /*
-- 
1.8.3.1