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From:   Christophe Leroy <christophe.leroy@csgroup.eu>
To:     Benjamin Herrenschmidt <benh@kernel.crashing.org>,
        Paul Mackerras <paulus@samba.org>,
        Michael Ellerman <mpe@ellerman.id.au>
Cc:     Christophe Leroy <christophe.leroy@csgroup.eu>,
        linux-kernel@vger.kernel.org, linuxppc-dev@lists.ozlabs.org
Subject: [PATCH] powerpc: align address to page boundary in change_page_attr()
Date:   Mon, 21 Mar 2022 16:44:45 +0100
Message-Id: <6bb118fb2ee89fa3c1f9cf90ed19f88220002cb0.1647877467.git.christophe.leroy@csgroup.eu>
MIME-Version: 1.0
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Aligning address to page boundary allows flush_tlb_kernel_range()
to know it's a single page flush and use tlbie instead of tlbia.

On 603 we now have the following code in first leg of
change_page_attr():

	  2c:	55 29 00 3c 	rlwinm  r9,r9,0,0,30
	  30:	91 23 00 00 	stw     r9,0(r3)
	  34:	7c 00 22 64 	tlbie   r4,r0
	  38:	7c 00 04 ac 	hwsync
	  3c:	38 60 00 00 	li      r3,0
	  40:	4e 80 00 20 	blr

Before we had:

	  28:	55 29 00 3c 	rlwinm  r9,r9,0,0,30
	  2c:	91 23 00 00 	stw     r9,0(r3)
	  30:	54 89 00 26 	rlwinm  r9,r4,0,0,19
	  34:	38 84 10 00 	addi    r4,r4,4096
	  38:	7c 89 20 50 	subf    r4,r9,r4
	  3c:	28 04 10 00 	cmplwi  r4,4096
	  40:	41 81 00 30 	bgt     70 <change_page_attr+0x70>
	  44:	7c 00 4a 64 	tlbie   r9,r0
	  48:	7c 00 04 ac 	hwsync
	  4c:	38 60 00 00 	li      r3,0
	  50:	4e 80 00 20 	blr
	...
	  70:	94 21 ff f0 	stwu    r1,-16(r1)
	  74:	7c 08 02 a6 	mflr    r0
	  78:	90 01 00 14 	stw     r0,20(r1)
	  7c:	48 00 00 01 	bl      7c <change_page_attr+0x7c>
				7c: R_PPC_REL24	_tlbia
	  80:	80 01 00 14 	lwz     r0,20(r1)
	  84:	38 60 00 00 	li      r3,0
	  88:	7c 08 03 a6 	mtlr    r0
	  8c:	38 21 00 10 	addi    r1,r1,16
	  90:	4e 80 00 20 	blr

Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
---
 arch/powerpc/mm/pageattr.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/powerpc/mm/pageattr.c b/arch/powerpc/mm/pageattr.c
index 85753e32a4de..6163e484bc6d 100644
--- a/arch/powerpc/mm/pageattr.c
+++ b/arch/powerpc/mm/pageattr.c
@@ -31,6 +31,7 @@ static int change_page_attr(pte_t *ptep, unsigned long addr, void *data)
 {
 	long action = (long)data;
 
+	addr &= PAGE_MASK;
 	/* modify the PTE bits as desired */
 	switch (action) {
 	case SET_MEMORY_RO:
-- 
2.35.1