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Date:   Mon, 21 Mar 2022 12:21:48 +0100
From:   Michael Walle <michael@walle.cc>
To:     netdev@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Clause 45 and Clause 22 PHYs on one MDIO bus
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Hi,

I have a board with a c22 phy (microchip lan8814) and a c45 phy
(intel/maxlinear gyp215) on one bus. If I understand it correctly, both
accesses should be able to coexist on one bus. But the microchip lan8814
actually has a bug and gets confused by c45 accesses. For example it 
will
respond in the middle of another transaction with its own data if it
decodes it as a read. That is something we can see on a logic analyzer.
But we also see random register writes on the lan8814 (which you don't 
see
on the logic analyzer obviously). Fortunately, the GPY215 supports 
indirect
MMD access by the standard c22 registers. Thus as a workaround for the
problem, we could have a c22 only mdio bus.

The SoC I'm using is the LAN9668, which uses the mdio-mscc-mdio driver.
First problem there, it doesn't support C45 (yet) but also doesn't check
for MII_ADDR_C45 and happily reads/writes bogus registers.

I've looked at the mdio subsystem in linux, there is probe_capabilities
(MDIOBUS_C45 and friends) but the mxl-gpy.c is using c45 accesses
nevertheless. I'm not sure if this is a bug or not.

I was thinking of a fallback mechanism for the c45 read access like
in read_mmd. And even if the mdio controller is c45 capable, a PHY
might opt out. In my case, the lan8814.

What do you think?

-michael