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Date:   Tue, 22 Mar 2022 08:46:22 +0100
From:   Marc Kleine-Budde <mkl@pengutronix.de>
To:     Pavel Pisa <pisa@cmp.felk.cvut.cz>
Cc:     linux-can@vger.kernel.org, devicetree@vger.kernel.org,
        Oliver Hartkopp <socketcan@hartkopp.net>,
        Wolfgang Grandegger <wg@grandegger.com>,
        David Miller <davem@davemloft.net>,
        Rob Herring <robh+dt@kernel.org>, mark.rutland@arm.com,
        Carsten Emde <c.emde@osadl.org>, armbru@redhat.com,
        netdev@vger.kernel.org, linux-kernel@vger.kernel.org,
        Marin Jerabek <martin.jerabek01@gmail.com>,
        Ondrej Ille <ondrej.ille@gmail.com>,
        Jiri Novak <jnovak@fel.cvut.cz>,
        Jaroslav Beran <jara.beran@gmail.com>,
        Petr Porazil <porazil@pikron.com>, Pavel Machek <pavel@ucw.cz>,
        Drew Fustini <pdp7pdp7@gmail.com>
Subject: Re: [PATCH v8 0/7] CTU CAN FD open-source IP core SocketCAN driver,
 PCI, platform integration and documentation
Message-ID: <20220322074622.5gkjhs25epurecvx@pengutronix.de>
References: <cover.1647904780.git.pisa@cmp.felk.cvut.cz>
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On 22.03.2022 00:32:27, Pavel Pisa wrote:
> This driver adds support for the CTU CAN FD open-source IP core.
> More documentation and core sources at project page
> (https://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core).
> The core integration to Xilinx Zynq system as platform driver
> is available (https://gitlab.fel.cvut.cz/canbus/zynq/zynq-can-sja1000-top=
).
> Implementation on Intel FPGA based PCI Express board is available
> from project (https://gitlab.fel.cvut.cz/canbus/pcie-ctucanfd).
> The CTU CAN FD core emulation send for review for QEMU mainline.
> Development repository for QEMU emulation - ctu-canfd branch of
>   https://gitlab.fel.cvut.cz/canbus/qemu-canbus
>=20
> More about CAN bus related projects used and developed at CTU FEE
> on the guidepost page http://canbus.pages.fel.cvut.cz/ .

The driver looks much better now. Good work. Please have a look at the
TX path of the mcp251xfd driver, especially the tx_stop_queue and
tx_wake_queue in mcp251xfd_start_xmit() and mcp251xfd_handle_tefif(). A
lockless implementation should work in your hardware, too.

BTW: The PROP_SEG/PHASE_SEG1 issue is known:

> +A curious reader will notice that the durations of the segments PROP_SEG
> +and PHASE_SEG1 are not determined separately but rather combined and
> +then, by default, the resulting TSEG1 is evenly divided between PROP_SEG
> +and PHASE_SEG1.

and the flexcan IP core in CAN-FD mode has the same problem. When
working on the bit timing parameter, I'll plan to have separate
PROP_SEG/PHASE_SEG1 min/max in the kernel, so that the bit timing
algorithm can take care of this.

regards,
Marc

--=20
Pengutronix e.K.                 | Marc Kleine-Budde           |
Embedded Linux                   | https://www.pengutronix.de  |
Vertretung West/Dortmund         | Phone: +49-231-2826-924     |
Amtsgericht Hildesheim, HRA 2686 | Fax:   +49-5121-206917-5555 |

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