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Date:   Tue, 22 Mar 2022 15:53:47 +0800
From:   Xin Ji <xji@analogixsemi.com>
To:     Pin-yen Lin <treapking@chromium.org>
Cc:     Andrzej Hajda <andrzej.hajda@intel.com>,
        Neil Armstrong <narmstrong@baylibre.com>,
        Robert Foss <robert.foss@linaro.org>,
        Laurent Pinchart <Laurent.pinchart@ideasonboard.com>,
        Jonas Karlman <jonas@kwiboo.se>,
        Jernej Skrabec <jernej.skrabec@gmail.com>,
        David Airlie <airlied@linux.ie>,
        Daniel Vetter <daniel@ffwll.ch>, treapking@google.com,
        qwen@analogixsemi.com, linux-kernel@vger.kernel.org,
        dri-devel@lists.freedesktop.org, hsinyi@chromium.org,
        bliang@analogixsemi.com
Subject: Re: drm/bridge: anx7625: Set downstream sink into normal status
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On Tue, Mar 22, 2022 at 03:33:17PM +0800, Pin-yen Lin wrote:
> Hi Xin,
> 
> Can we use dev_dbg instead of dev_info for the logging?
> 
> The log here is more like a debugging message, and using dev_dbg makes
> it consistent with anx7625_dp_stop.
> 
> Sorry for not catching this earlier.
> 
> Best regards,
> Pin-yen
Hi Pin-yen, OK, I'll change it in next version.
Thanks,
Xin
> 
> On Thu, Mar 3, 2022 at 3:52 PM Pin-yen Lin <treapking@chromium.org> wrote:
> >
> > Reviewed-by: Pin-Yen Lin <treapking@chromium.org>
> >
> >
> > On Wed, Mar 2, 2022 at 8:09 PM Xin Ji <xji@analogixsemi.com> wrote:
> > >
> > > As downstream sink was set into standby mode while bridge disabled,
> > > this patch used for setting downstream sink into normal status
> > > while enable bridge.
> > >
> > > Signed-off-by: Xin Ji <xji@analogixsemi.com>
> > > ---
> > >  drivers/gpu/drm/bridge/analogix/anx7625.c | 8 ++++++++
> > >  1 file changed, 8 insertions(+)
> > >
> > > diff --git a/drivers/gpu/drm/bridge/analogix/anx7625.c b/drivers/gpu/drm/bridge/analogix/anx7625.c
> > > index 9aab879a8851..963eaf73ecab 100644
> > > --- a/drivers/gpu/drm/bridge/analogix/anx7625.c
> > > +++ b/drivers/gpu/drm/bridge/analogix/anx7625.c
> > > @@ -919,12 +919,20 @@ static void anx7625_dp_start(struct anx7625_data *ctx)
> > >  {
> > >         int ret;
> > >         struct device *dev = &ctx->client->dev;
> > > +       u8 data;
> > >
> > >         if (!ctx->display_timing_valid) {
> > >                 DRM_DEV_ERROR(dev, "mipi not set display timing yet.\n");
> > >                 return;
> > >         }
> > >
> > > +       dev_info(dev, "set downstream sink into normal\n");
> > > +       /* Downstream sink enter into normal mode */
> > > +       data = 1;
> > > +       ret = anx7625_aux_trans(ctx, DP_AUX_NATIVE_WRITE, 0x000600, 1, &data);
> > > +       if (ret < 0)
> > > +               dev_err(dev, "IO error : set sink into normal mode fail\n");
> > > +
> > >         /* Disable HDCP */
> > >         anx7625_write_and(ctx, ctx->i2c.rx_p1_client, 0xee, 0x9f);
> > >