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Received: from BN6PR1201MB0178.namprd12.prod.outlook.com (2603:10b6:405:55::20) by MN2PR12MB4239.namprd12.prod.outlook.com (2603:10b6:208:1d2::11) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5081.16; Tue, 22 Mar 2022 08:38:18 +0000 Received: from BN6PR1201MB0178.namprd12.prod.outlook.com ([fe80::944e:aab8:facf:fd8]) by BN6PR1201MB0178.namprd12.prod.outlook.com ([fe80::944e:aab8:facf:fd8%8]) with mapi id 15.20.5081.023; Tue, 22 Mar 2022 08:38:17 +0000 Message-ID: <7de451b4-32ff-c8b5-7c69-6440f73b59ae@amd.com> Date: Tue, 22 Mar 2022 14:07:58 +0530 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:91.0) Gecko/20100101 Thunderbird/91.7.0 Subject: Re: [PATCH 6/7] perf/x86/amd/core: Add PerfMonV2 overflow handling Content-Language: en-US To: Like Xu Cc: peterz@infradead.org, bp@alien8.de, dave.hansen@linux.intel.com, acme@kernel.org, mark.rutland@arm.com, alexander.shishkin@linux.intel.com, namhyung@kernel.org, jolsa@kernel.org, tglx@linutronix.de, mingo@redhat.com, pbonzini@redhat.com, jmattson@google.com, eranian@google.com, ananth.narayan@amd.com, ravi.bangoria@amd.com, santosh.shukla@amd.com, "linux-kernel@vger.kernel.org" , linux-perf-users@vger.kernel.org, x86@kernel.org References: <7d43b4ba8a7c3c0833495f3fabfcfc6df8db3732.1647498015.git.sandipan.das@amd.com> <4bc9b537-f0de-5b75-5418-61c1d6dca849@gmail.com> From: Sandipan Das In-Reply-To: <4bc9b537-f0de-5b75-5418-61c1d6dca849@gmail.com> Content-Type: text/plain; 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> > The variable 'val' set but not used. > >> +        mask = BIT_ULL(idx); >> + >> +        if (!(status & mask)) > > Needed here ? > If you are referring to this previous usage of 'val' within x86_pmu_handle_irq(): if (val & (1ULL << (x86_pmu.cntval_bits - 1))) then, no. Instead of looking at bit 47 of the raw counter value, one can look at the overflow bits of the global status register to determine if a counter overflow has occurred. Will remove 'val' as you suggested since it is no longer needed for any decision making.