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Date:   Tue, 22 Mar 2022 16:32:42 -0700
From:   Pawan Gupta <pawan.kumar.gupta@linux.intel.com>
To:     Borislav Petkov <bp@alien8.de>,
        Thomas Gleixner <tglx@linutronix.de>
Cc:     Ingo Molnar <mingo@redhat.com>,
        Dave Hansen <dave.hansen@linux.intel.com>, x86@kernel.org,
        "H. Peter Anvin" <hpa@zytor.com>, Andi Kleen <ak@linux.intel.com>,
        Tony Luck <tony.luck@intel.com>, linux-kernel@vger.kernel.org,
        antonio.gomez.iglesias@linux.intel.com, neelima.krishnan@intel.com,
        stable@vger.kernel.org, Andrew Cooper <Andrew.Cooper3@citrix.com>,
        Josh Poimboeuf <jpoimboe@redhat.com>
Subject: Re: [PATCH v2 0/2] TSX update
Message-ID: <20220322233242.mlslvnucjb5sjyk2@guptapa-desk>
References: <cover.1646943780.git.pawan.kumar.gupta@linux.intel.com>
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Hi Boris and others,

On Thu, Mar 10, 2022 at 01:59:47PM -0800, Pawan Gupta wrote:
>v2:
>- Added patch to disable TSX development mode (Andrew, Boris)
>- Rebased to v5.17-rc7
>
>v1: https://lore.kernel.org/lkml/5bd785a1d6ea0b572250add0c6617b4504bc24d1.1644440311.git.pawan.kumar.gupta@linux.intel.com/
>
>Hi,
>
>After a recent microcode update some Intel processors will always abort
>Transactional Synchronization Extensions (TSX) transactions [*]. On
>these processors a new CPUID bit,
>CPUID.07H.0H.EDX[11](RTM_ALWAYS_ABORT), will be enumerated to indicate
>that the loaded microcode is forcing Restricted Transactional Memory
>(RTM) abort. If the processor enumerated support for RTM previously, the
>CPUID enumeration bits for TSX (CPUID.RTM and CPUID.HLE) continue to be
>set by default after the microcode update.
>
>First patch in this series clears CPUID.RTM and CPUID.HLE so that
>userspace doesn't enumerate TSX feature.
>
>Microcode also added support to re-enable TSX for development purpose,
>doing so is not recommended for production deployments, because MD_CLEAR
>flows for the mitigation of TSX Asynchronous Abort (TAA) may not be
>effective on these processors when TSX is enabled with updated
>microcode.
>
>Second patch unconditionally disables this TSX development mode, in case
>it was enabled by the software running before kernel boot.
>
>Thanks,
>Pawan
>
>[*] Intel Transactional Synchronization Extension (Intel TSX) Disable Update for Selected Processors
>    https://cdrdv2.intel.com/v1/dl/getContent/643557
>
>Pawan Gupta (2):
>  x86/tsx: Use MSR_TSX_CTRL to clear CPUID bits
>  x86/tsx: Disable TSX development mode at boot

I am hoping to get some feedback on v2. Are these patches looking okay?

Thanks,
Pawan