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From:   Alexander Stein <alexander.stein@ew.tq-group.com>
To:     p.zabel@pengutronix.de, l.stach@pengutronix.de,
        bhelgaas@google.com, lorenzo.pieralisi@arm.com, robh@kernel.org,
        shawnguo@kernel.org, vkoul@kernel.org,
        Richard Zhu <hongxing.zhu@nxp.com>
Cc:     linux-phy@lists.infradead.org, devicetree@vger.kernel.org,
        linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
        linux-kernel@vger.kernel.org, kernel@pengutronix.de,
        linux-imx@nxp.com, Richard Zhu <hongxing.zhu@nxp.com>
Subject: Re: (EXT) [PATCH v2 6/7] arm64: dts: imx8mp-evk: Add PCIe support
Date:   Thu, 24 Mar 2022 11:04:35 +0100
Message-ID: <2236205.ElGaqSPkdT@steina-w>
Organization: TQ-Systems GmbH
In-Reply-To: <1646644054-24421-7-git-send-email-hongxing.zhu@nxp.com>
References: <1646644054-24421-1-git-send-email-hongxing.zhu@nxp.com> <1646644054-24421-7-git-send-email-hongxing.zhu@nxp.com>
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Hello Richard,

thanks for providing PCIe support for iMX8MP.

Am Montag, 7. M=E4rz 2022, 10:07:33 CET schrieb Richard Zhu:
> Add PCIe support on i.MX8MP EVK board.
>=20
> Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
> ---
>  arch/arm64/boot/dts/freescale/imx8mp-evk.dts | 55 ++++++++++++++++++++
>  1 file changed, 55 insertions(+)
>=20
> diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
> b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts index
> 2eb943210678..ed77455a3f73 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
> +++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
> @@ -5,6 +5,7 @@
>=20
>  /dts-v1/;
>=20
> +#include <dt-bindings/phy/phy-imx8-pcie.h>
>  #include "imx8mp.dtsi"
>=20
>  / {
> @@ -33,6 +34,12 @@ memory@40000000 {
>  		      <0x1 0x00000000 0 0xc0000000>;
>  	};
>=20
> +	pcie0_refclk: pcie0-refclk {
> +		compatible =3D "fixed-clock";
> +			#clock-cells =3D <0>;
> +			clock-frequency =3D <100000000>;
> +	};
> +
>  	reg_can1_stby: regulator-can1-stby {
>  		compatible =3D "regulator-fixed";
>  		regulator-name =3D "can1-stby";
> @@ -55,6 +62,17 @@ reg_can2_stby: regulator-can2-stby {
>  		enable-active-high;
>  	};
>=20
> +	reg_pcie0: regulator-pcie {
> +		compatible =3D "regulator-fixed";
> +		pinctrl-names =3D "default";
> +		pinctrl-0 =3D <&pinctrl_pcie0_reg>;
> +		regulator-name =3D "MPCIE_3V3";
> +		regulator-min-microvolt =3D <3300000>;
> +		regulator-max-microvolt =3D <3300000>;
> +		gpio =3D <&gpio2 6 GPIO_ACTIVE_HIGH>;
> +		enable-active-high;
> +	};
> +
>  	reg_usdhc2_vmmc: regulator-usdhc2 {
>  		compatible =3D "regulator-fixed";
>  		pinctrl-names =3D "default";
> @@ -297,6 +315,30 @@ pca6416: gpio@20 {
>  	};
>  };
>=20
> +&pcie_phy {
> +	fsl,refclk-pad-mode =3D <IMX8_PCIE_REFCLK_PAD_INPUT>;
> +	clocks =3D <&pcie0_refclk>;
> +	clock-names =3D "ref";
> +	status =3D "okay";
> +};
> +
> +&pcie{
> +	pinctrl-names =3D "default";
> +	pinctrl-0 =3D <&pinctrl_pcie0>;
> +	reset-gpio =3D <&gpio2 7 GPIO_ACTIVE_LOW>;
> +	clocks =3D <&clk IMX8MP_CLK_HSIO_ROOT>,
> +		 <&clk IMX8MP_CLK_PCIE_ROOT>,
> +		 <&clk IMX8MP_CLK_HSIO_AXI>;
> +	clock-names =3D "pcie", "pcie_aux", "pcie_bus";

This causes the following warnings in dtbs_check (paths stripped):
imx8mp-evk.dtb: pcie@33800000: clock-names:1: 'pcie_bus' was expected
        From schema: Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.y=
aml
imx8mp-evk.dtb: pcie@33800000: clock-names:2: 'pcie_phy' was expected
        From schema: Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.y=
aml

The bindings want 4 clocks for imx8mq (and imx8mp which seems similar):
* pcie
* pcie_bus
* pcie_phy
* pcie_aux

Ignoring the order there is no pcie_phy clock anymore, it was removed in=20
commit 1840518ae7de ("clk: imx8mp: Remove the none exist pcie clocks"). I w=
as=20
wondering why, because the PCIE_PHY_CLK_ROOT at register 0xa380 inside CCM =
is=20
listed in RM.
So there is a clock missing for 'pcie_phy' or the binding needs some update=
=20
for imx8mp, no?

Regards,
Alexander

> +	assigned-clocks =3D <&clk IMX8MP_CLK_HSIO_AXI>,
> +			  <&clk IMX8MP_CLK_PCIE_AUX>;
> +	assigned-clock-rates =3D <500000000>, <10000000>;
> +	assigned-clock-parents =3D <&clk IMX8MP_SYS_PLL2_500M>,
> +				 <&clk IMX8MP_SYS_PLL2_50M>;
> +	vpcie-supply =3D <&reg_pcie0>;
> +	status =3D "okay";
> +};
> +
>  &snvs_pwrkey {
>  	status =3D "okay";
>  };
> @@ -442,6 +484,19 @@ MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA		0x400001c3
>=20
>  		>;
>=20
>  	};
>=20
> +	pinctrl_pcie0: pcie0grp {
> +		fsl,pins =3D <
> +			MX8MP_IOMUXC_I2C4_SCL__PCIE_CLKREQ_B=09
0x61 /* open drain, pull up */
> +			MX8MP_IOMUXC_SD1_DATA5__GPIO2_IO07=09
0x41
> +		>;
> +	};
> +
> +	pinctrl_pcie0_reg: pcie0reggrp {
> +		fsl,pins =3D <
> +			MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06=09
0x41
> +		>;
> +	};
> +
>  	pinctrl_pmic: pmicgrp {
>  		fsl,pins =3D <
>  			MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03=09
0x000001c0